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authorRocky Phagura <rphagura@fb.com>2020-10-08 13:32:41 -0700
committerArthur Heymans <arthur@aheymans.xyz>2020-11-24 12:44:28 +0000
commit17a798b68cc6d475d5d0c14e1a4a39b14754203c (patch)
tree756939e4342122d76eb74b71a552c7360b591fcd /LICENSES
parentf4721246db125e08b5e60a8a38a08cb92c478bd3 (diff)
soc/intel/xeon_sp: Enable SMI handler
SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura@fb.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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