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authorJincheng Li <jincheng.li@intel.com>2024-03-13 15:06:26 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-03-26 10:10:48 +0000
commit31998020458af821cb61d0000ee2cbd0293958f6 (patch)
tree280829f2d75b7c2582f4d5ad5308e7fdebbcd635 /LICENSES/HPND.txt
parente17113a3f3f3d6ccf5f79bea7c405e983860bc52 (diff)
soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms
DDR support codes across generations are similar. Share the codes to improve code reuse. TEST=intel/archercity CRB Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81219 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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