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authorKeith Short <keithshort@chromium.org>2019-05-06 16:12:57 -0600
committerDuncan Laurie <dlaurie@chromium.org>2019-05-22 14:21:57 +0000
commit7006458777483291abfca790beb48f201ba74c37 (patch)
tree51b74ce035d0869dae3ef61d0f9de8e156862ae6 /Documentation
parentba44a27f7fcc50677e2b0789f61fce2df8f6d620 (diff)
post_code: add post code for failure to load next stage
Add a new post code, POST_INVALID_ROM, used when coreboot fails to locate or validate a resource that is stored in ROM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/POSTCODES1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES
index 5d337b629d..2340fac049 100644
--- a/Documentation/POSTCODES
+++ b/Documentation/POSTCODES
@@ -16,6 +16,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
0x66 Devices have been enumerated
0x88 Devices have been configured
0x89 Devices have been enabled
+0xe0 Boot media (e.g. SPI ROM) is corrupt
0xf8 Entry into elf boot
0xf3 Jumping to payload