diff options
author | Riku Viitanen <riku.viitanen@protonmail.com> | 2023-05-02 00:47:32 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-07-03 05:01:02 +0000 |
commit | 685097ba3befd40be833f4a8eb43637462d984e4 (patch) | |
tree | 963276a8de49fde7f254ba76dfd287c64e4aa551 /Documentation | |
parent | 8d16a14367e8f8f887811d070aa18e138850a11f (diff) |
mb/hp: Add new port for compaq_8300_elite_usdt
New port based on autoport.
Autoport worked with minor tweaks, but fan speeds went almost
immediately to the maximum. They are controlled by the NPCD379
Super I/O which isn't supported by coreboot.
But coreboot already has code for NPCD378,
which HP Compaq 8200 SFF makes use of.
So SuperIO configuration was copied from the 8200 SFF port.
It seems to work without any issues in "normal" use.
Most importantly, fan speed control seems to work correctly.
However this means that some of the SuperIO LDNs may be configured
incorrectly. See the comments on Gerrit for more information.
The following is tested and is working:
* Native raminit with both DIMMs
* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
* External USB2 and USB3 ports: they all work
* USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports)
* Ethernet
* Mini-PCIe WLAN
* SATA: 2.5" SSD and optical drive bay
* Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1
* GRUB (with Libreboot config)
* PS/2 keyboard and mouse
* S3 suspend and resume, wake using USB keyboard
* Headphone output, line out, internal speaker
* Wake on LAN
* Rebooting
* CMOS options & nvramcui
Untested:
* mSATA slot. The SATA port needs to be enabled on devicetree
too, but I'm unable to test due to lack of hardware
* Line in, mic input
* MXM graphics card
* EHCI debug
Not working:
* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
maybe it just isn't present
* PS/2 keyboard wake from S3
Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/mainboard/hp/compaq_8300_usdt.md | 66 | ||||
-rw-r--r-- | Documentation/mainboard/hp/compaq_8300_usdt_rom_header.jpg | bin | 0 -> 151377 bytes |
2 files changed, 66 insertions, 0 deletions
diff --git a/Documentation/mainboard/hp/compaq_8300_usdt.md b/Documentation/mainboard/hp/compaq_8300_usdt.md new file mode 100644 index 0000000000..1d4a0c7e8b --- /dev/null +++ b/Documentation/mainboard/hp/compaq_8300_usdt.md @@ -0,0 +1,66 @@ +# HP Compaq 8300 Elite USDT + +This page describes how to run coreboot on the [Compaq 8300 Elite USDT] desktop +from [HP]. + +## Flashing coreboot + +```eval_rst ++---------------------+-------------+ +| Type | Value | ++=====================+=============+ +| Socketed flash | no | ++---------------------+-------------+ +| Model | W25Q128BVFG | ++---------------------+-------------+ +| Size | 16 MiB | ++---------------------+-------------+ +| In circuit flashing | yes | ++---------------------+-------------+ +| Package | SOIC-16 | ++---------------------+-------------+ +| Write protection | No | ++---------------------+-------------+ +| Dual BIOS feature | No | ++---------------------+-------------+ +``` + +### Internal programming + +TODO: investigate + +The board has two jumpers that might be relevant: FDO (Flash Descriptor Override) and BB (?). + +### External programming + +Remove the lid. The flash chip can be found on the edge opposite to the CPU. +There is a spot for a "ROM RCVRY" header next to the flash chip but it is +unpopulated. If you don't feel like using a clip, you can easily solder +a standard pin header there yourself and use it for programming. + +Programming powers some parts of the board. Programming when +Wake on LAN is active works great. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| SuperIO | NPCD379HAKFX | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +### SuperIO + +This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work +fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`. + +[Compaq 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866 +[HP]: https://www.hp.com/ diff --git a/Documentation/mainboard/hp/compaq_8300_usdt_rom_header.jpg b/Documentation/mainboard/hp/compaq_8300_usdt_rom_header.jpg Binary files differnew file mode 100644 index 0000000000..967f91ca30 --- /dev/null +++ b/Documentation/mainboard/hp/compaq_8300_usdt_rom_header.jpg |