diff options
| author | Evgeny Zinoviev <me@ch1p.com> | 2020-03-22 19:08:15 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-09 07:48:13 +0000 |
| commit | b08543a6400db38516c2b424f4838c4cd6b70ca0 (patch) | |
| tree | 8452cdac7e150aa4850ecfc4f30234e318b7c210 /Documentation | |
| parent | d2b3961fdc951f2dbbec22c7dce68fc0337112cc (diff) | |
Doc/mb/lenovo/montevina_series: Use Makefile to generate IFD
util/bincfg's Makefile already has target that generates flash
descriptor. Use it instead.
Change-Id: I1756514e1ab7b64de23a98314d8a32e9258e648c
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/mainboard/lenovo/montevina_series.md | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index f3aca04adf..529fec679a 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -112,9 +112,11 @@ If your flash is not 8 MiB, you need to change values of `flcomp_density1` and Then create the flash descriptor: ```console -$ ./bincfg ifd-x200.spec ifd-x200.set ifd.bin +$ make gen-ifd-x200 ``` +It will be saved to the `flashregion_0_fd.bin` file. + #### Configuring coreboot Now configure coreboot. You need to select correct chip size and specify paths @@ -127,7 +129,7 @@ Mainboard ---> Chipset ---> [*] Add Intel descriptor.bin file - # Note: if you used bincfg, specify path to generated util/bincfg/ifd.bin + # Note: if you used bincfg, specify path to generated util/bincfg/flashregion_0_fd.bin (/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file [*] Add gigabit ethernet configuration |