soc/intel/xeon_sp: Remove NO_FSP_TEMP_RAM_EXIT from common config

For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not
be selected.

Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

0 files changed, 0 insertions, 0 deletions