diff options
| author | Nicholas Chin <nic.c3.14@gmail.com> | 2024-09-07 22:42:44 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-09 23:26:42 +0000 |
| commit | b5401a6266f1bfd7f02eb3c483646c600bf8083b (patch) | |
| tree | 564e8f09e722b90e55e4f60b97d2cec35b792f15 /Documentation/soc/intel | |
| parent | 41251a0445d0ce306f239674b18c22106875d303 (diff) | |
Docs: Revert false MyST Parser toctree conversions
Commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser)
converted recommonmark style toctrees in bulk using a script. This was
done by searching for lists of references, which is how recommonmark
denoted toctree entries. However, this also converted lists of external
URLs, which would not normally be included in the toctree. Revert these
cases back to lists of URLs as they were before the migration.
Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'Documentation/soc/intel')
| -rw-r--r-- | Documentation/soc/intel/fit.md | 8 | ||||
| -rw-r--r-- | Documentation/soc/intel/fsp/index.md | 36 | ||||
| -rw-r--r-- | Documentation/soc/intel/fsp/ppi/ppi.md | 12 |
3 files changed, 10 insertions, 46 deletions
diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md index d2629b4614..b7dbc5f8bc 100644 --- a/Documentation/soc/intel/fit.md +++ b/Documentation/soc/intel/fit.md @@ -56,9 +56,5 @@ execution of the IA32 reset vector happens. ## References -```{toctree} -:maxdepth: 1 - -Intel TXT LAB handout <https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf> -FIT BIOS specification <https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf> -``` +* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf) +* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf) diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 6d29aca63b..8359bcbac9 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -65,35 +65,15 @@ those are fixed. If possible a workaround is described here as well. ## Open Source Intel FSP specification -```{toctree} -:maxdepth: 1 - -About Intel FSP <https://firmware.intel.com/learn/fsp/about-intel-fsp> -``` - -```{toctree} -:maxdepth: 1 - -FSP Specification 1.0 <https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf> -``` - -```{toctree} -:maxdepth: 1 +* [About Intel FSP](https://firmware.intel.com/learn/fsp/about-intel-fsp) -FSP Specification 1.1 <https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf> -``` - -```{toctree} -:maxdepth: 1 +* [FSP Specification 1.0](https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf) -FSP Specification 2.0 <https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf> -``` +* [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf) -```{toctree} -:maxdepth: 1 +* [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf) -FSP Specification 2.1 <https://cdrdv2.intel.com/v1/dl/getContent/611786> -``` +* [FSP Specification 2.1](https://cdrdv2.intel.com/v1/dl/getContent/611786) ## Additional Features in FSP 2.1 specification @@ -105,11 +85,7 @@ PPI <ppi/ppi.md> ## Official bugtracker -```{toctree} -:maxdepth: 1 - -IntelFSP/FSP <https://github.com/IntelFsp/FSP/issues> -``` +- [IntelFSP/FSP](https://github.com/IntelFsp/FSP/issues) [Issue 10]: https://github.com/IntelFsp/FSP/issues/10 [Issue 13]: https://github.com/IntelFsp/FSP/issues/13 diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md index bb14af04e6..6d7afb47d4 100644 --- a/Documentation/soc/intel/fsp/ppi/ppi.md +++ b/Documentation/soc/intel/fsp/ppi/ppi.md @@ -6,17 +6,9 @@ chipset using Intel FSP. This feature is added into FSP specification 2.1 where FSP should be able to locate PPI, published by boot firmware and able to execute the same in FSP's context. -```{toctree} -:maxdepth: 1 - -What is PPI <https://www.intel.com/content/dam/www/public/us/en/documents/reference-guides/efi-pei-cis-v09.pdf> -``` +* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference-guides/efi-pei-cis-v09.pdf) ## List of PPI service ### Publish MP Service PPI from boot firmware (coreboot) to initialize CPU -```{toctree} -:maxdepth: 1 - -MP Service PPI <mp_service_ppi.md> -``` +- [MP Service PPI](mp_service_ppi.md) |