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authorMatt DeVillier <matt.devillier@gmail.com>2023-10-19 20:31:08 -0500
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2023-10-31 15:03:28 +0000
commit1cbdb205d94a024570895d31c413609544f62a54 (patch)
tree030bc6154a841b5ca66e48e52b9ad667c8edb151 /Documentation/rmodules.md
parent6dba745cc8627b0a316141f16a6662890e2cb419 (diff)
soc/intel/tigerlake: Implement SoC sleep state array
Copied from Alderlake implementation, modified as needed for Tigerlake. Device names missing from soc_acpi_name() were added as well. TEST=build/boot Win11, Linux on google/volteer (drobit). Change-Id: I34999891ea0d386328698109b6315d481de7c43a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78521 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
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