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| author | Huayang Duan <huayang.duan@mediatek.com> | 2019-11-20 13:51:47 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 17:57:03 +0000 |
| commit | 6ee5559d6a3c1ba452a53db58ec6b41d629d92b2 (patch) | |
| tree | b59d973bc534adfd4fad17301e0e2d2222a9d7ac /Documentation/releases/coreboot-4.9-relnotes.md | |
| parent | 6de7ecb585e705beab32e7464d364f2284ccae54 (diff) | |
soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps to improve DRAM stability.
BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'Documentation/releases/coreboot-4.9-relnotes.md')
0 files changed, 0 insertions, 0 deletions