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authorFurquan Shaikh <furquan@google.com>2020-05-04 20:59:23 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-11 23:27:25 +0000
commitefe27cf3f978e7510b272a28b59779bc387c8106 (patch)
tree4aee70ba783d2339d06cff92211225c872f087bc /Documentation/releases/coreboot-4.11-relnotes.md
parent235a75128ab7642247bf0895a15c698c63eb13ba (diff)
soc/amd/common/block/lpc: Add config options for eSPI
eSPI on Picasso is configured using the LPC bridge configuration registers. This change enables config options to allow SoC to select if it supports eSPI (SOC_AMD_COMMON_BLOCK_HAS_ESPI) and mainboard to select if it wants to use eSPI instead of LPC for talking to legacy devices and embedded controllers (SOC_AMD_COMMON_BLOCK_USE_ESPI). BUG=b:154445472 Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41069 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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