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authorJohn Zhao <john.zhao@intel.com>2020-05-01 22:04:00 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-07-07 17:29:56 +0000
commit5d16a25e0cece666e9275a1c627050bfd918b6ac (patch)
tree2f6bbc3a8bcf9ddce34ae8dac94cdff20eea9e35 /Documentation/payloads.md
parentcb01c2a315d20ca0eb0269b7917a9884d7f4c2fd (diff)
soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master
This change disables Thunderbolt PCIe root ports bus master before handing over to payload in order to mitigate the threat from the unauthorized external DMA. In this state, the PCIe root ports would be considered as trusted to not forward any DMA transactions to downstream endpoint devices. BUG=b:141609884 TEST=Verified PCIe resource has been allocated properly and USB behind Thunderbolt dock is enumerated successfully. Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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