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| author | Rory Liu <rory.liu@quanta.corp-partner.google.com> | 2021-12-30 11:36:45 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-03 16:15:39 +0000 |
| commit | 2a4858afed4c8618182a78a6de965d1cad6e8630 (patch) | |
| tree | 49e51696970ef7118e9caf94aa923d24a5c4706f /Documentation/northbridge/intel | |
| parent | 69107c149b458be1ba7500d59686cdea066a0cae (diff) | |
mb/google/brya/var/brask: Change I2C/DDC signals
The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14,
I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12.
BUG=b:206602609
TEST=build pass
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Diffstat (limited to 'Documentation/northbridge/intel')
0 files changed, 0 insertions, 0 deletions