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author | Tristan Corrick <tristan@corrick.kiwi> | 2018-12-21 23:47:03 +1300 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-24 08:16:06 +0000 |
commit | cbc561f64a5dc5ca4489703ba96b7ec91d840bf7 (patch) | |
tree | b0dc86c5d685e9f5cc12abd66f7d673b2db911db /Documentation/northbridge/intel/haswell/mrc.bin.md | |
parent | a26b02466ec3b089346215906720b60d50382554 (diff) |
Documentation/nb/intel: Add Haswell documentation
At the moment, this just gives some details on the MRC.
Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'Documentation/northbridge/intel/haswell/mrc.bin.md')
-rw-r--r-- | Documentation/northbridge/intel/haswell/mrc.bin.md | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md new file mode 100644 index 0000000000..e27e9d6c61 --- /dev/null +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -0,0 +1,35 @@ +# mrc.bin + +All Haswell boards supported by coreboot currently require a proprietary +blob in order to initialise the DRAM and a few other components. The +blob, named `mrc.bin`, largely consists of Intel's memory reference code +(MRC), but it has been tailored specifically for Chrome OS. It is just +under 200 KiB in size. Another name for `mrc.bin` is the system agent +binary. + +Having a replacement for `mrc.bin` using native coreboot code is very +much desired, but it is not an easy task. + +## Obtaining mrc.bin + +Unfortunately, it is not currently possible to distribute `mrc.bin` as +part of coreboot. Though, it can be obtained from a Haswell Chromebook +or Chromebox firmware image, and you might find one online. `mrc.bin` +can be extracted with the following command. If extracting from a +"standard" coreboot image, omit `-r RO_SECTION`. + +```bash +cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION +``` + +Now, place `mrc.bin` in the root of the coreboot directory. +Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to +its location when building coreboot. + +## ECC DRAM + +When `mrc.bin` has finished executing, ECC is active on the channels +populated with ECC DIMMs. However, `mrc.bin` was tailored specifically +for Haswell Chromebooks and Chomeboxes, none of which support ECC DRAM. +While ECC likely functions correctly, it is advised to further validate +the correct operation of ECC if data integrity is absolutely critical. |