diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2015-12-02 12:25:37 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-16 12:00:03 +0100 |
| commit | 0ab8e00aebd360b5b99690de4948004dc2738770 (patch) | |
| tree | f2f60ec16ab9569e20fb92036354cdae178fce93 /Documentation/mainboard_io_trap_handler_sample.c | |
| parent | 086730b0629237c9f171515b82b617ef27f73492 (diff) | |
google/lars: Disable SD 3.0 Controller [D30:F6]
LARs design don't have SD Connector over native SD Controller.
BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot LARs. Use "lspci" doesn't list 0x1E:06
device in list.
CQ-DEPEND=CL:315420
Change-Id: Idff7243a6aaf4b8d5f49e4bf215a77131f716485
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca769138b97b404598c4a6bfa6c2ff5c1c3ec896
Original-Change-Id: I71416ac89a8c91ab272d6737d1b46c8045567e17
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12947
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/mainboard_io_trap_handler_sample.c')
0 files changed, 0 insertions, 0 deletions