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| author | Philipp Hug <philipp@hug.cx> | 2019-04-04 15:57:24 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-04-23 09:34:09 +0000 |
| commit | 6b6dc6eddd8e31a99167b19219a20cca115df3cc (patch) | |
| tree | 0aac3bf0eacf778e5526a83b961a7db9241d1a08 /Documentation/mainboard/sifive | |
| parent | 7f1a0e6b4c6a319d3cd552c708195d94b99bbb97 (diff) | |
hifive-unleashed: update documentation to match current state
Signed-off-by: Philipp Hug <philipp@hug.cx>
Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'Documentation/mainboard/sifive')
| -rw-r--r-- | Documentation/mainboard/sifive/hifive-unleashed.md | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index cd7c93ca0b..495dade212 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -12,15 +12,13 @@ For general setup instructions, please refer to the [Getting Started Guide]. The following things are still missing from this coreboot port: - Support running romstage from flash (fix stack) to support boot mode 1 -- CBMEM support -- FU540 clock configuration -- FU540 RAM init -- Placing the ramstage in DRAM - Starting the U54 cores - FU540 PIN configuration and GPIO access macros - Provide serial number to payload (e.g. in device tree) +- Implement instruction emulation - Support for booting Linux on RISC-V - +- Add support to run OpenSBI payload in m-mode +- SMP support in trap handler ## Configuration |