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authorSubrata Banik <subratabanik@google.com>2022-02-11 13:58:31 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-02-26 00:15:28 +0000
commit4de2c342fbfe2d96afe1f4d6ccd9be22367aacad (patch)
tree2d4b5cab8ef5f0259d5d32ee51cec6b970f02f99 /Documentation/mainboard/purism/librem_mini_flash.jpg
parent737ad67d122b24f8309ad76b66b5d7a26873eb39 (diff)
soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
This fixes no practical problem, especially for coreboot where only one process should access the SPI controller. It makes the code look more spec compliant. As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. Software must initiate the next SPI transaction when this bit is 0. Add non-blocking mechanism with `5sec` timeout to report back error if current SPI transaction is failing due to on-going SPI access. BUG=b:215255210 TEST=Able to boot brya and verified SPI read/write is successful. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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