Documentation: Fix header levels

This fixes the following MyST Parser warnings:

- Non-consecutive header level increase
- Document headings start at H2, not H1

The header levels (the number of "#" characters before a heading) are
intended to form a logical hierarchy of each section and subsection in a
document. A subsection typically should have a header level one more
than its parent section. Most of these warnings are caused by extra "#"
characters, which were simply removed, or sections missing a "#"
character to make it fall under its parent section.

Notable changes:

getting_started/kconfig.md: Changed the header level of the "Keywords"
section from 2 to 3 to fall under "Kconfig Language" (level 2), and
increased the level of each keyword from 3 to 4 to remain under
"Keywords". This also fixes the warnings of "H3 to H5" increases, since
the Usage/Example/Notes/Restrictions sections for each keyword had a
level of 5.

soc/intel/cse_fw_update/cse_fw_update.md: Changed the first line to a
top level header acting as the title of the document. Without this
soc/intel/index.md displays all the level 2 headers in this document
instead of a single link to cse_fw_update.md.

Change-Id: Ia1f8b52e39b7b6524bef89a95365541235b5b1b9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83382
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>

1 files changed, 3 insertions, 3 deletions

diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md
index e4e5da3c5f..120a161e90 100644
--- a/Documentation/mainboard/lenovo/montevina_series.md
+++ b/Documentation/mainboard/lenovo/montevina_series.md
@@ -46,7 +46,7 @@ Now you need to patch the flash descriptor. You can either [modify the one from
 your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
 [use one from the coreboot repository](#using-checked-in-flash-descriptor-via-bincfg).
 
-#### Modifying flash descriptor using ifdtool
+### Modifying flash descriptor using ifdtool
 
 Pick the layout according to your chip size from the table below and save it to
 the `new_layout.txt` file:
@@ -88,7 +88,7 @@ $ mv flashregion_0_flashdescriptor.bin.new.new flashregion_0_flashdescriptor.bin
 
 Continue to the [Configuring coreboot](#configuring-coreboot) section.
 
-#### Using checked-in flash descriptor via bincfg
+### Using checked-in flash descriptor via bincfg
 
 There is a copy of an X200's flash descriptor checked into the coreboot
 repository. It is supposed to work for the T400/T500 as well. The descriptor
@@ -119,7 +119,7 @@ $ make gen-ifd-x200
 
 It will be saved to the `flashregion_0_fd.bin` file.
 
-#### Configuring coreboot
+### Configuring coreboot
 
 Now configure coreboot. You need to select correct chip size and specify paths
 to flash descriptor and gbe dump.