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authorMichał Zieliński <michal.zielinski@posteo.net>2024-10-17 20:48:50 +0200
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2024-11-20 22:14:18 +0000
commitf30d11ccd712a7e06803dfe6224eb468de054de7 (patch)
treeea97b8377c57396464137aeece6c3d0f7c5e140a /Documentation/mainboard/hp
parent1c75aa7d00a523dec7eafe15050681d43629e960 (diff)
mb/hp: Add HP Compaq 8300 Elite SFF
* Add initial board commit based on HP 8200 SFF and HP Z220 SFF. * Add documentation. Tested on HP 8300 SFF. Change-Id: Ib5322acc0210f000b53954e2925549358f86d5c8 Signed-off-by: Michał Zieliński <michal.zielinski@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67666 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
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+# HP Compaq 8300 Elite SFF
+
+This page describes how to run coreboot on the [Compaq 8300 Elite SFF] desktop
+from [HP].
+
+## TODO
+
+The following things are still missing from this coreboot port:
+
+- Extended HWM reporting
+- Advanced LED control
+- Advanced power configuration in S3
+
+## Flashing coreboot
+
+```{eval-rst}
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | no |
++---------------------+------------+
+| Model | MT25QL128 |
++---------------------+------------+
+| Size | 16 MiB |
++---------------------+------------+
+| In circuit flashing | yes |
++---------------------+------------+
+| Package | SOIC-16 |
++---------------------+------------+
+| Write protection | Yes |
++---------------------+------------+
+| Dual BIOS feature | No |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+```
+
+### Internal programming
+
+Internal flashing is possible. The SPI flash can be accessed using [flashrom],
+but you have to short the FDO pins located near the rear USB3 ports on the
+motherboard using a jumper, to temporarily disable write protections while on the
+stock firmware. Once the coreboot rom is flashed, one should remove the jumper.
+
+### External programming
+
+External programming with an SPI adapter and [flashrom] does work, but it powers the
+whole southbridge complex. You need to supply enough current through the programming adapter.
+
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
+
+## Technology
+
+```{eval-rst}
++------------------+--------------------------------------------------+
+| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge | bd82x6x |
++------------------+--------------------------------------------------+
+| CPU | model_206ax |
++------------------+--------------------------------------------------+
+| SuperIO | :doc:`../../superio/nuvoton/npcd378` |
++------------------+--------------------------------------------------+
+| EC | |
++------------------+--------------------------------------------------+
+| Coprocessor | Intel ME |
++------------------+--------------------------------------------------+
+```
+
+[Compaq 8300 Elite SFF]: https://support.hp.com/us-en/document/c03345460
+[HP]: https://www.hp.com/
+[flashrom]: https://flashrom.org/Flashrom