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author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-08-31 10:03:32 +0800 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-02 15:31:34 +0000 |
commit | 14bb6f5dab90500c7d37b06f0588123bd4c58ffd (patch) | |
tree | 32e8bbb0891f3ded9b8e2fa48b67a37065bcb1a8 /Documentation/mainboard/gigabyte | |
parent | f496286bdce061fce5a54a8ea2befbaf2ebdb12a (diff) |
mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet
Enable PCIE port 7 using clk 6 for RTL8125 Ethernet
BUG=b:193750191
BRANCH=None
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'Documentation/mainboard/gigabyte')
0 files changed, 0 insertions, 0 deletions