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| author | Frans Hendriks <fhendriks@eltan.com> | 2018-10-31 10:07:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-28 11:46:43 +0000 |
| commit | f01a15952adb903fed169dbcef1e4a33cc88ba3f (patch) | |
| tree | b7eea269144cf2be3b4a15c5974f9aa5604a9146 /Documentation/hypertransport.svg | |
| parent | ad19c2f58bcf30af87795543d5667d47e421558e (diff) | |
src/soc/intel/braswell/acpi/lpc.asl: Add ACPI and GPIO bases
ACPI and GPIO base are used by LPC controller, but not reserved.
Both bases are added to the LPC device resources.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5248694b497c4965d79dd7c25ec97592dc0dddbc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'Documentation/hypertransport.svg')
0 files changed, 0 insertions, 0 deletions