diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-04 23:32:41 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-28 16:39:50 +0200 |
| commit | 01ae11b057e4b15e1fde48c7845f7fbf66a4e948 (patch) | |
| tree | b98863dcb2d5afae537e244048d25027b55f3c35 /Documentation/hypertransport.svg | |
| parent | 2ee54db24603f51738cbebd6d80c120f2b4db76d (diff) | |
soc/intel/common/block: Add Intel common systemagent support
Create common Intel systemagent code.
This code currently contains the SA initialization
required in Bootblock phase, which has the following programming-
* Set PCIEXBAR
* Clear TSEG register
More code will get added up in the subsequent phases.
Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'Documentation/hypertransport.svg')
0 files changed, 0 insertions, 0 deletions