soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+

On Alder Lake, Meteor Lake and Panther Lake platforms the way size to
consider for NEM+ computation is the effective way size.

On Alder Lake, the External Design Specification #627270 "3.5.2
No-Eviction Mode (NEM) Sizes" provides a way to compute the effective
way size by reading the number of CBO. Unfortunately, reading the
number of CBO is not possible on Meteor Lake and Panther
Lake. Therefore, we instead compute the effective way size as the
biggest of power of two of the way size which works across all three
platforms.

The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to
control this behavior.

The issue addressed by this commit can be observed with the following
experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to
0x400000 (4 MB).

The number of ways that used to be computed is round(0x400000 /
0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000
NEM+ region. When the bootblock code accesses memory between 3 MB and
4 MB, the core would raise a page fault exception.

The right computation is: 0x400000 / eff_way_size(0x180000) = 4. 4
ways needs to be mapped to cover the entire 0x400000 NEM+ region.

BUG=b:360332771
TEST=Verified on PTL Intel reference platform

Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

0 files changed, 0 insertions, 0 deletions