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| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-09-22 19:07:21 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-13 15:21:48 +0000 |
| commit | 2188f57a806feb7b25816d70919f12e5e2ba84b3 (patch) | |
| tree | a24b2c92ff1821c0b988f5f6dffe66a3a78190b7 /Documentation/build_system.md | |
| parent | c8374e32920d2bffbd5fe7b65621fe0b90cfb19e (diff) | |
src/device: Update LTR configuration scheme
This patch moves out LTR programming under L1 substate
to pchexp_tune_device function, as substate programming
and LTR programming are independent.
LTR programming scheme is updated to scan through entire
tree and enable LTR mechanism on pci device if LTR mechanism
is supported by device.
BRANCH=none
BUG=b:66722364
TEST=Verify LTR is configured for end point devices and max
snoop latency gets configured.
Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/21868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'Documentation/build_system.md')
0 files changed, 0 insertions, 0 deletions