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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-29 09:57:05 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 16:36:26 +0000
commit2ec1c13ac4a9724095ce71783fd52f70a0b1536d (patch)
treedf15407f69cfc7899aa06ad3f35dec32164c4d07 /Documentation/beginverbatim.tex
parentb887adf7a56f2877c41e808002f30841a6679eb6 (diff)
soc/intel/common: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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