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| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-14 13:22:01 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-09-17 19:58:00 +0000 |
| commit | e5ec50c2363602ccb72a988365063987b9ea3e09 (patch) | |
| tree | ff7c12cfe6abe6cc3059c5f1b28c2b8e64078005 /Documentation/arch/riscv | |
| parent | a3cb3220185cf47a59a1b8b74d3a4fcdef5e57b6 (diff) | |
nb/intel/haswell: Guard DMIBAR/EPBAR macro parameters
Add brackets around the parameters to avoid operation order problems.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I5e1a02ba2ebf468f0d80b7f1838766280b6b7b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45352
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/arch/riscv')
0 files changed, 0 insertions, 0 deletions