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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-12 14:01:13 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:56:36 +0000 |
| commit | 56f768774a25320d738febf99c335abdb6eeafbe (patch) | |
| tree | 4c6def307e71cc2d096c5152d86c6d396e09ea73 /Documentation/arch/riscv | |
| parent | 724c66c88fa219087f4d6a0ccce1ba1d6f93c93b (diff) | |
soc/intel/broadwell: Use the common cpu/intel/car romstage entry
The only functional difference is the use of stack guards.
Change-Id: I95645271e0d93a97f544a1cc4e9a4320738e6a20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'Documentation/arch/riscv')
0 files changed, 0 insertions, 0 deletions