diff options
author | Keith Short <keithshort@chromium.org> | 2019-05-09 11:40:34 -0600 |
---|---|---|
committer | Duncan Laurie <dlaurie@chromium.org> | 2019-05-22 17:44:53 +0000 |
commit | 15588b03b36aa875e2a2a31cc649a2d9dff7581e (patch) | |
tree | 70c054b070ca0b4f962b362d06ff62ef8a7454e9 /Documentation/POSTCODES | |
parent | 24302633a558e545efcc84178136bd1879f6d8ee (diff) |
post_code: add post code for hardware initialization failure
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to
detect or initialize a required hardware component.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'Documentation/POSTCODES')
-rw-r--r-- | Documentation/POSTCODES | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 2a8285b27f..a9d392a9b0 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -20,6 +20,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0xe1 Resource stored within CBFS is corrupt 0xe2 Vendor binary (e.g. FSP) generated a fatal error 0xe3 RAM could not be initialized +0xe4 Critical hardware component could not initialize 0xf8 Entry into elf boot 0xf3 Jumping to payload |