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authorFurquan Shaikh <furquan@google.com>2020-05-04 21:22:22 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-11 23:27:46 +0000
commit1e279a5cb2d0e2388023885f6d073ef6eb56dde9 (patch)
treefdfacd6bd04ed25da84b182faa207873be8875e6 /Documentation/Intel/fsp1_1.html
parentefe27cf3f978e7510b272a28b59779bc387c8106 (diff)
soc/amd/common/block/lpc: Reorganize LPC enable resources
This change moves all the logic for setting up decode windows for LPC under configure_child_lpc_windows() which is called from lpc_enable_children_resources(). This is in preparation to configure decode windows for eSPI differently if mainboard decides to use eSPI instead of LPC. Side-effect of this change is that the IO decode registers are written after each child device resources are considered. BUG=b:154445472 Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41070 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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