diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-01-07 11:24:24 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-02 15:54:43 +0100 |
| commit | c1e4f8995362c6eb7d09dfc0618edcc636d30acc (patch) | |
| tree | f5639a152232579412a3a9da0e4cd224f30505e8 /Documentation/Intel/Board/board.html | |
| parent | 2f91403303a66c5e724761a74863e3452291b154 (diff) | |
Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for
x86.
TEST=None
Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/Intel/Board/board.html')
| -rw-r--r-- | Documentation/Intel/Board/board.html | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html new file mode 100644 index 0000000000..e43985c62d --- /dev/null +++ b/Documentation/Intel/Board/board.html @@ -0,0 +1,83 @@ +<!DOCTYPE html> +<html> + <head> + <title>Board</title> + </head> + <body> + +<h1>x86 Board Development</h1> +<p> + Board development requires System-on-a-Chip (SoC) support. + The combined steps are listed + <a target="_blank" href="../x86Development.html">here</a>. + The development steps for the board are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the board directory as src/mainboard/<Vendor>/<Board>. +</p> + +<p> + The following files are required to build a new board: +</p> +<ol> + <li>Kconfig.name - Defines the Kconfig value for the board</li> + <li>Kconfig + <ol type="A"> + <li>Selects the SoC for the board and specifies the SPI flash size + <ol type="I"> + <li>BOARD_ROMSIZE_KB_<Size></li> + <li>SOC_<Vendor>_<Chip Family></li> + </ol> + </li> + <li>Declare the Kconfig values for: + <ol type="I"> + <li>MAINBOARD_DIR</li> + <li>MAINBOARD_PART_NUMBER</li> + <li>MAINBOARD_VENDOR</li> + </ol> + </li> + </ol> + </li> + <li>devicetree.cb - Enable root bridge and serial port + <ol type="A"> + <li>The first line must be "chip soc/Intel/<soc family>"; + this path is used by the generated static.c to include the chip.h + header file + </li> + </ol> + </li> + <li>romstage.c + <ol type="A"> + <li>Add routine mainboard_romstage_entry which calls romstage_common</li> + </ol> + </li> + <li>Configure coreboot build: + <ol type="A"> + <li>Set LOCALVERSION</li> + <li>FLASHMAP_OFFSET = 0x00700000</li> + <li>Select vendor for the board</li> + <li>Select the board</li> + <li>CBFS_SIZE = 0x00100000</li> + <li>Set the CPU_MICROCODE_CBFS_LEN</li> + <li>Set the CPU_MICROCODE_CBFS_LOC</li> + <li>Set the FSP_IMAGE_ID_STRING</li> + <li>Set the FSP_LOC</li> + <li>Disable GOP_SUPPORT</li> + <li>No payload</li> + <li>Choose the default value for all other options</li> + </ol> + </li> +</ol> + + +<hr> +<p>Modified: 31 January 2016</p> + </body> +</html>
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