From c1e4f8995362c6eb7d09dfc0618edcc636d30acc Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 7 Jan 2016 11:24:24 -0800 Subject: Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/Board/board.html | 83 ++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/Intel/Board/board.html (limited to 'Documentation/Intel/Board/board.html') diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html new file mode 100644 index 0000000000..e43985c62d --- /dev/null +++ b/Documentation/Intel/Board/board.html @@ -0,0 +1,83 @@ + + + + Board + + + +

x86 Board Development

+

+ Board development requires System-on-a-Chip (SoC) support. + The combined steps are listed + here. + The development steps for the board are listed below: +

+
    +
  1. Required Files
    2. +
+ + +
+

Required Files

+

+ Create the board directory as src/mainboard/<Vendor>/<Board>. +

+ +

+ The following files are required to build a new board: +

+
    +
  1. Kconfig.name - Defines the Kconfig value for the board
    2. +
  2. Kconfig +
      +
    1. Selects the SoC for the board and specifies the SPI flash size +
        +
      1. BOARD_ROMSIZE_KB_<Size>
        2. +
      2. SOC_<Vendor>_<Chip Family>
        3. +
      +
      2. +
    2. Declare the Kconfig values for: +
        +
      1. MAINBOARD_DIR
        2. +
      2. MAINBOARD_PART_NUMBER
        3. +
      3. MAINBOARD_VENDOR
        4. +
      +
      3. +
    +
    3. +
  3. devicetree.cb - Enable root bridge and serial port +
      +
    1. The first line must be "chip soc/Intel/<soc family>"; + this path is used by the generated static.c to include the chip.h + header file +
      2. +
    +
    4. +
  4. romstage.c +
      +
    1. Add routine mainboard_romstage_entry which calls romstage_common
      2. +
    +
    5. +
  5. Configure coreboot build: +
      +
    1. Set LOCALVERSION
      2. +
    2. FLASHMAP_OFFSET = 0x00700000
      3. +
    3. Select vendor for the board
      4. +
    4. Select the board
      5. +
    5. CBFS_SIZE = 0x00100000
      6. +
    6. Set the CPU_MICROCODE_CBFS_LEN
      7. +
    7. Set the CPU_MICROCODE_CBFS_LOC
      8. +
    8. Set the FSP_IMAGE_ID_STRING
      9. +
    9. Set the FSP_LOC
      10. +
    10. Disable GOP_SUPPORT
      11. +
    11. No payload
      12. +
    12. Choose the default value for all other options
      13. +
    +
    6. +
+ + +
+

Modified: 31 January 2016

+ + \ No newline at end of file -- cgit v1.2.3