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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-15 10:21:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-14 07:41:11 +0000 |
| commit | 840c27ecfccc1cdb75ae2d0c11da54efb8c5676a (patch) | |
| tree | 1a226abb85117da17c56e65570d6305b43c91dbc /Documentation/Doxyfile.coreboot_simple | |
| parent | a2cc23169a81f669fa38ebf0f6b1393b06c17fda (diff) | |
nb/intel/x4x/raminit: Make programming crossclock support DDR3
A few values were wrong, but it does not seem to matter all that
much.
Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19871
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/Doxyfile.coreboot_simple')
0 files changed, 0 insertions, 0 deletions