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| author | CK Hu <ck.hu@mediatek.com> | 2020-04-07 12:06:31 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-08-13 05:34:18 +0000 |
| commit | 958ab46ddae6bf906e4db3d499ca719c019c78c8 (patch) | |
| tree | 86b396c82767fbedc7391f42bf9a22e1d09fbbea /Documentation/Doxyfile.coreboot | |
| parent | 5559a449d4c02b3652d9e5294f4a0550686afbcf (diff) | |
soc/mediatek/mt8192: Add DRAM resource in ramstage
Add DRAM resource in ramstage to load payload.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'Documentation/Doxyfile.coreboot')
0 files changed, 0 insertions, 0 deletions