Make SB600/SB700 more similar for easier diffs (trivial).

Also fixes random whitespace issues, typos, etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed, 53 insertions, 68 deletions

diff --git a/src/southbridge/amd/rs690/chip.h b/src/southbridge/amd/rs690/chip.h
index 6ae3dd5a0f..5e08cc59f8 100644
--- a/src/southbridge/amd/rs690/chip.h
+++ b/src/southbridge/amd/rs690/chip.h
@@ -20,13 +20,13 @@
 #ifndef RS690_CHIP_H
 #define RS690_CHIP_H
 
-/* Member variables are defined in Config.lb. */
+/* Member variables are defined in devicetree.cb. */
 struct southbridge_amd_rs690_config
 {
 	u8 gpp_configuration;	/* The configuration of General Purpose Port, A/B/C/D/E. */
 	u8 port_enable;		/* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
 	u8 gfx_dev2_dev3;	/* for GFX Core initialization REFCLK_SEL */
-	u8 gfx_dual_slot;		/* Is it dual graphics slots */
+	u8 gfx_dual_slot;	/* Is it dual graphics slots */
 	u8 gfx_lane_reversal;	/* Single/Dual slot lan reversal */
 	u8 gfx_tmds;		/* whether support TMDS? */
 	u8 gfx_compliance;	/* whether support compliance? */
diff --git a/src/southbridge/amd/rs780/chip.h b/src/southbridge/amd/rs780/chip.h
index fa72a01e31..87053f24a9 100644
--- a/src/southbridge/amd/rs780/chip.h
+++ b/src/southbridge/amd/rs780/chip.h
@@ -20,7 +20,7 @@
 #ifndef RS780_CHIP_H
 #define RS780_CHIP_H
 
-/* Member variables are defined in Config.lb. */
+/* Member variables are defined in devicetree.cb. */
 struct southbridge_amd_rs780_config
 {
 	u8 gppsb_configuration;		/* The configuration of General Purpose Port, A/B/C/D/E. */
diff --git a/src/southbridge/amd/sb600/sb600.c b/src/southbridge/amd/sb600/sb600.c
index d9b3dcc9e4..61a0c6559c 100644
--- a/src/southbridge/amd/sb600/sb600.c
+++ b/src/southbridge/amd/sb600/sb600.c
@@ -120,21 +120,21 @@ void sb600_enable(device_t dev)
 
 	printk(BIOS_DEBUG, "sb600_enable()\n");
 
-/*
-*	0:12.0  SATA	bit 8 of sm_dev 0xac : 1 - enable, default         + 32 * 3
-*	0:13.1  USB-1	bit 2 of sm_dev 0x68
-*	0:13.2  USB-2	bit 3 of sm_dev 0x68
-*	0:13.3  USB-3	bit 4 of sm_dev 0x68
-*	0:13.4  USB-4	bit 5 of sm_dev 0x68
-*	0:13.5  USB2	bit 0 of sm_dev 0x68 : 1 - enable, default
-*	0:14.0  SMBUS							0
-*	0:14.1  IDE							1
-*	0:14.2  HDA	bit 3 of pm_io 0x59 : 1 - enable, default	    + 32 * 4
-*	0:14.3  LPC	bit 20 of sm_dev 0x64 : 0 - disable, default  + 32 * 1
-*	0:14.4  PCI							4
-*	0:14.5  ACI	bit 0 of pm_io 0x59 : 0 - enable, default
-*	0:14.6  MCI	bit 1 of pm_io 0x59 : 0 - enable, default
-*/
+	/*
+	 * 0:12.0  SATA	bit 8 of sm_dev 0xac : 1 - enable, default         + 32 * 3
+	 * 0:13.1  USB-1	bit 2 of sm_dev 0x68
+	 * 0:13.2  USB-2	bit 3 of sm_dev 0x68
+	 * 0:13.3  USB-3	bit 4 of sm_dev 0x68
+	 * 0:13.4  USB-4	bit 5 of sm_dev 0x68
+	 * 0:13.5  USB2	bit 0 of sm_dev 0x68 : 1 - enable, default
+	 * 0:14.0  SMBUS							0
+	 * 0:14.1  IDE							1
+	 * 0:14.2  HDA	bit 3 of pm_io 0x59 : 1 - enable, default	    + 32 * 4
+	 * 0:14.3  LPC	bit 20 of sm_dev 0x64 : 0 - disable, default  + 32 * 1
+	 * 0:14.4  PCI							4
+	 * 0:14.5  ACI	bit 0 of pm_io 0x59 : 0 - enable, default
+	 * 0:14.6  MCI	bit 1 of pm_io 0x59 : 0 - enable, default
+	 */
 	if (dev->device == 0x0000) {
 		vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
 		deviceid = (vendorid >> 16) & 0xffff;
diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c
index a6888269f7..0fefd4ef45 100644
--- a/src/southbridge/amd/sb600/sb600_early_setup.c
+++ b/src/southbridge/amd/sb600/sb600_early_setup.c
@@ -25,7 +25,6 @@
 #define SMBUS_IO_BASE 0x1000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */
 
-
 static void pmio_write(u8 reg, u8 value)
 {
 	outb(reg, PM_INDEX);
@@ -38,7 +37,7 @@ static u8 pmio_read(u8 reg)
 	return inb(PM_INDEX + 1);
 }
 
-/* Get SB ASIC Revision.*/
+/* RPR 2.1: Get SB ASIC Revision. */
 static u8 get_sb600_revision(void)
 {
 	device_t dev;
@@ -131,22 +130,21 @@ static u32 get_sbdn(u32 bus)
 	return (dev >> 15) & 0x1f;
 }
 
-
 static u8 dual_core(void)
 {
 	return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0;
 }
 
 /*
-SB600 VFSMAF (VID/FID System Management Action Field)  is 010b by default.
-RPR 2.3.3 C-state and VID/FID change for the K8 platform.
+ * SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
+ * RPR 2.3.3 C-state and VID/FID change for the K8 platform.
 */
 static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 {
 	u8 byte;
 	byte = pmio_read(0x9a);
 	byte &= ~0x34;
-	if(dual_core())
+	if (dual_core())
 		byte |= 0x34;
 	else
 		byte |= 0x04;
@@ -170,11 +168,11 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	byte |= 0x01;
 	pmio_write(0x7c, byte);
 
-	/*Must be 0 for K8 platform.*/
+	/* Must be 0 for K8 platform. */
 	byte = pmio_read(0x68);
 	byte &= ~0x01;
 	pmio_write(0x68, byte);
-	/*Must be 0 for K8 platform.*/
+	/* Must be 0 for K8 platform. */
 	byte = pmio_read(0x8d);
 	byte &= ~(1<<6);
 	pmio_write(0x8d, byte);
@@ -187,7 +185,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	byte &= ~0x04;
 	pmio_write(0x42, byte);
 
-	if(get_sb600_revision() == 0x14) {
+	if (get_sb600_revision() == 0x14) {
 		pmio_write(0x89, 0x10);
 
 		byte = pmio_read(0x52);
@@ -196,7 +194,6 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	}
 }
 
-
 void hard_reset(void)
 {
 	set_bios_reset();
@@ -277,7 +274,6 @@ void sb600_lpc_port80(void)
 	pci_write_config8(dev, 0x4a, byte);
 }
 
-
 /* sbDevicesPorInitTable */
 static void sb600_devices_por_init(void)
 {
diff --git a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
index 723cc2d839..64b016e0d6 100644
--- a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
@@ -20,14 +20,12 @@
 #include <usbdebug.h>
 
 #ifndef SB600_DEVN_BASE
-
 #define SB600_DEVN_BASE 0
-
 #endif
 
-#define EHCI_BAR_INDEX 0x10
-#define EHCI_BAR 0xFEF00000
-#define EHCI_DEBUG_OFFSET 0xE0
+#define EHCI_BAR_INDEX		0x10
+#define EHCI_BAR		0xFEF00000
+#define EHCI_DEBUG_OFFSET	0xE0
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
@@ -39,5 +37,5 @@ static void sb600_enable_usbdebug(u32 port)
 	set_debug_port(port);
 	pci_write_config32(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5),
 			   EHCI_BAR_INDEX, EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enabe */
+	pci_write_config8(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enable */
 }
diff --git a/src/southbridge/amd/sb600/sb600_hda.c b/src/southbridge/amd/sb600/sb600_hda.c
index 3ba1fe910e..1768350686 100644
--- a/src/southbridge/amd/sb600/sb600_hda.c
+++ b/src/southbridge/amd/sb600/sb600_hda.c
@@ -151,6 +151,7 @@ static u32 cim_verb_data[] = {
 	0x01f71ec4,
 	0x01f71f01,
 };
+
 static u32 find_verb(u32 viddid, u32 ** verb)
 {
 	device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
@@ -171,7 +172,6 @@ static u32 find_verb(u32 viddid, u32 ** verb)
  *  Wait 50usec for for the codec to indicate it is ready
  *  no response would imply that the codec is non-operative
  */
-
 static int wait_for_ready(u32 base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
@@ -194,7 +194,6 @@ static int wait_for_ready(u32 base)
  *  the previous command.  No response would imply that the code
  *  is non-operative
  */
-
 static int wait_for_valid(u32 base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
@@ -301,7 +300,7 @@ static void hda_init(struct device *dev)
 	if (!res)
 		return;
 
-	base = ((u32)res->base);
+	base = (u32)res->base;
 	printk(BIOS_DEBUG, "base = 0x%x\n", base);
 	codec_mask = codec_detect(base);
 
diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c
index 6a18bfeea5..66e93e6e33 100644
--- a/src/southbridge/amd/sb600/sb600_sm.c
+++ b/src/southbridge/amd/sb600/sb600_sm.c
@@ -327,10 +327,10 @@ static void sb600_sm_read_resources(device_t dev)
 	res->gran = 8;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
 
-
 	compact_resources(dev);
 
 }
+
 static void sb600_sm_set_resources(struct device *dev)
 {
 	struct resource *res;
@@ -338,7 +338,6 @@ static void sb600_sm_set_resources(struct device *dev)
 
 	pci_dev_set_resources(dev);
 
-
 	/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
 	byte = pm_ioread(0x52);
 	byte |= 1 << 6;
@@ -357,6 +356,7 @@ static void sb600_sm_set_resources(struct device *dev)
 static struct pci_operations lops_pci = {
 	.set_subsystem = pci_dev_set_subsystem,
 };
+
 static struct device_operations smbus_ops = {
 	.read_resources = sb600_sm_read_resources,
 	.set_resources = sb600_sm_set_resources,
@@ -367,6 +367,7 @@ static struct device_operations smbus_ops = {
 	.ops_pci = &lops_pci,
 	.ops_smbus_bus = &lops_smbus_bus,
 };
+
 static const struct pci_driver smbus_driver __pci_driver = {
 	.ops = &smbus_ops,
 	.vendor = PCI_VENDOR_ID_ATI,
diff --git a/src/southbridge/amd/sb600/sb600_smbus.c b/src/southbridge/amd/sb600/sb600_smbus.c
index 8174ce8d44..0cc0e62c04 100644
--- a/src/southbridge/amd/sb600/sb600_smbus.c
+++ b/src/southbridge/amd/sb600/sb600_smbus.c
@@ -114,8 +114,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
 	return 0;
 }
 
-int do_smbus_read_byte(u32 smbus_io_base, u32 device,
-			      u32 address)
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
 {
 	u8 byte;
 
@@ -145,8 +144,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device,
 	return byte;
 }
 
-int do_smbus_write_byte(u32 smbus_io_base, u32 device,
-			       u32 address, u8 val)
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
 {
 	u8 byte;
 
@@ -176,8 +174,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device,
 	return 0;
 }
 
-static void alink_ab_indx(u32 reg_space, u32 reg_addr,
-			  u32 mask, u32 val)
+static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
 {
 	u32 tmp;
 
diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c
index 22f804ac23..d667143ded 100644
--- a/src/southbridge/amd/sb700/sb700_early_setup.c
+++ b/src/southbridge/amd/sb700/sb700_early_setup.c
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef  _SB700_EARLY_SETUP_C_
-#define  _SB700_EARLY_SETUP_C_
+#ifndef _SB700_EARLY_SETUP_C_
+#define _SB700_EARLY_SETUP_C_
 
 #include <reset.h>
 #include <arch/cpu.h>
@@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg)
 	return inb(PM_INDEX + 1);
 }
 
-/* RPR 2.28 Get SB ASIC Revision.*/
+/* RPR 2.28: Get SB ASIC Revision. */
 static u8 set_sb700_revision(void)
 {
 	device_t dev;
@@ -195,11 +195,11 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	byte |= 0x03;
 	pmio_write(0x7c, byte);
 
-	/*Must be 0 for K8 platform.*/
+	/* Must be 0 for K8 platform. */
 	byte = pmio_read(0x68);
 	byte &= ~0x01;
 	pmio_write(0x68, byte);
-	/*Must be 0 for K8 platform.*/
+	/* Must be 0 for K8 platform. */
 	byte = pmio_read(0x8d);
 	byte &= ~(1<<6);
 	pmio_write(0x8d, byte);
diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
index 746cc4306a..06bcab77a3 100644
--- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
@@ -20,14 +20,12 @@
 #include <usbdebug.h>
 
 #ifndef SB700_DEVN_BASE
-
 #define SB700_DEVN_BASE 0
-
 #endif
 
-#define EHCI_BAR_INDEX 0x10
-#define EHCI_BAR 0xFEF00000
-#define EHCI_DEBUG_OFFSET 0xE0
+#define EHCI_BAR_INDEX		0x10
+#define EHCI_BAR		0xFEF00000
+#define EHCI_DEBUG_OFFSET	0xE0
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
@@ -39,5 +37,5 @@ static void sb700_enable_usbdebug(u32 port)
 	set_debug_port(port);
 	pci_write_config32(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5),
 			   EHCI_BAR_INDEX, EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enabe */
+	pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enable */
 }
diff --git a/src/southbridge/amd/sb700/sb700_ide.c b/src/southbridge/amd/sb700/sb700_ide.c
index d56362b03e..08e625492b 100644
--- a/src/southbridge/amd/sb700/sb700_ide.c
+++ b/src/southbridge/amd/sb700/sb700_ide.c
@@ -51,7 +51,7 @@ static void ide_init(struct device *dev)
 	pci_write_config16(dev, 0x4, dword);
 
 	/* set ide as primary, if you want to boot from IDE, you'd better set it
-	 * in mainboard/Config.lb */
+	 * in $vendor/$mainboard/devicetree.cb */
 	if (conf->boot_switch_sata_ide == 1) {
 		byte = pci_read_config8(dev, 0xAD);
 		byte |= 1 << 4;
diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/sb700_smbus.c
index 65e6912568..ee1653df3e 100644
--- a/src/southbridge/amd/sb700/sb700_smbus.c
+++ b/src/southbridge/amd/sb700/sb700_smbus.c
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef  _SB700_SMBUS_C_
-#define  _SB700_SMBUS_C_
+#ifndef _SB700_SMBUS_C_
+#define _SB700_SMBUS_C_
 
 #include "sb700_smbus.h"
 
@@ -90,8 +90,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
 	return byte;
 }
 
-int do_smbus_send_byte(u32 smbus_io_base, u32 device,
-			      u8 val)
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
 {
 	u8 byte;
 
@@ -118,8 +117,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device,
 	return 0;
 }
 
-int do_smbus_read_byte(u32 smbus_io_base, u32 device,
-			      u32 address)
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
 {
 	u8 byte;
 
@@ -149,8 +147,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device,
 	return byte;
 }
 
-int do_smbus_write_byte(u32 smbus_io_base, u32 device,
-			       u32 address, u8 val)
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
 {
 	u8 byte;
 
@@ -180,8 +177,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device,
 	return 0;
 }
 
-static void alink_ab_indx(u32 reg_space, u32 reg_addr,
-			  u32 mask, u32 val)
+static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
 {
 	u32 tmp;