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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2021-11-12 13:09:27 +0800
committerWerner Zeh <werner.zeh@siemens.com>2021-11-15 10:08:12 +0000
commitfb02f0a55e8aa0a1e73d907611f6cf51fa7e76ad (patch)
tree0e531f6e88e4953e45d5e47445779e9bfdd6a937
parent91c3ace5af5c0db5512554370bfbabe6b693156d (diff)
mb/google/brya/var/felwinter: Remove USB2 port 0
USB2 port 0 is empty as per schematics. BUG=b:206047996 TEST=USB2 port 0 is disabled. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/google/brya/variants/felwinter/overridetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 8420452c46..dedd192096 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -15,6 +15,7 @@ chip soc/intel/alderlake
.configure_ext_fivr = 1,
}"
+ register "usb2_ports[0]" = "USB2_PORT_EMPTY"
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb3_ports[3]" = "USB3_PORT_EMPTY"