diff options
author | Zhuohao Lee <zhuohao@chromium.org> | 2018-09-08 16:53:10 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-16 08:35:29 +0000 |
commit | fa61f5aa55fd1a84a8e0ea5d2e20df46cd15ae9b (patch) | |
tree | 53d0b2f60a8bc357bec9c0db6adb35aa141fb623 | |
parent | f89c56a54d62495804167eef40b2718cfdade185 (diff) |
mb/google/poppy/variants/rammus: fix S0ix entering issue
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and
CIO2 devices to avoid the system failed to enter S0ix.
BUG=b:114502527
BRANCH=master
TEST=On DUT, echo freeze > /sys/power/state
1. check the S0ix status on EC console
2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r-- | src/mainboard/google/poppy/variants/rammus/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 7c1b02ff93..3478744137 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -40,8 +40,8 @@ chip soc/intel/skylake register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" + register "Cio2Enable" = "0" + register "SaImguEnable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" |