intel/fsp_baytrail: Support Baytrail FSP Gold4 release

Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION
structure to include these new PCD options and initialized the setting
when given in devicetree.cb.

Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/10838
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>

3 files changed, 45 insertions, 3 deletions

diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
index 57e242737f..b69054d44f 100644..100755
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2014 Intel Corporation
+ * Copyright (C) 2014-2015 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -189,6 +189,38 @@ struct soc_intel_fsp_baytrail_config {
 	#define  TXE_UMA_DISABLE	UPD_DISABLE
 	#define  TXE_UMA_ENABLE		UPD_ENABLE
 
+	/*
+	 * PcdOsSelection
+	 * Selection 0x1 , "Android"
+	 * Selection 0x4 , "Linux OS"
+	 */
+	uint8_t  PcdOsSelection;
+	#define  OS_SELECTION_DEFAULT	UPD_DEFAULT
+	#define  OS_SELECTION_ANDROID	INCREMENT_FOR_DEFAULT(1)
+	#define  OS_SELECTION_LINUX	INCREMENT_FOR_DEFAULT(4)
+
+	/* PcdEMMC45DDR50Enabled */
+	uint8_t  PcdEMMC45DDR50Enabled;
+	#define  EMMC45_DDR50_DEFAULT	UPD_DEFAULT
+	#define  EMMC45_DDR50_DISABLE	UPD_DISABLE
+	#define  EMMC45_DDR50_ENABLE	UPD_ENABLE
+
+	/* PcdEMMC45HS200Enabled */
+	uint8_t  PcdEMMC45HS200Enabled;
+	#define  EMMC45_HS200_DEFAULT	UPD_DEFAULT
+	#define  EMMC45_HS200_DISABLE	UPD_DISABLE
+	#define  EMMC45_HS200_ENABLE	UPD_ENABLE
+
+	/* PcdEMMC45RetuneTimerValue */
+	uint8_t  PcdEMMC45RetuneTimerValue;
+	#define  EMMC45_RETURN_TIMER_DEFAULT UPD_DEFAULT
+
+	/* PcdEnableIgd */
+	uint8_t  PcdEnableIgd;
+	#define  ENABLE_IGD_DEFAULT	UPD_DEFAULT
+	#define  ENABLE_IGD_DISABLE	UPD_DISABLE
+	#define  ENABLE_IGD_ENABLE	UPD_ENABLE
+
 	/* Memory down data */
 	uint8_t  EnableMemoryDown;
 	#define  MEMORY_DOWN_DEFAULT	UPD_DEFAULT
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 0abab98c7c..ad85c5b8a5 100644..100755
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2014 Intel Corporation
+ * Copyright (C) 2014-2015 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -112,6 +112,11 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
 	UPD_DEFAULT_CHECK(PcdSccEnablePciMode);
 	UPD_DEFAULT_CHECK(IgdRenderStandby);
 	UPD_DEFAULT_CHECK(TxeUmaEnable);
+	UPD_DEFAULT_CHECK(PcdOsSelection);
+	UPD_DEFAULT_CHECK(PcdEMMC45DDR50Enabled);
+	UPD_DEFAULT_CHECK(PcdEMMC45HS200Enabled);
+	UPD_DEFAULT_CHECK(PcdEMMC45RetuneTimerValue);
+	UPD_DEFAULT_CHECK(PcdEnableIgd);
 
 	if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) ||
 			(config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE))
diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h
index 02de3cbd1c..76f7ce7b8a 100755
--- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h
+++ b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h
@@ -97,7 +97,12 @@ typedef struct _UPD_DATA_REGION {
   UINT8                       PcdSccEnablePciMode;           /* Offset 0x004D */
   UINT8                       IgdRenderStandby;              /* Offset 0x004E */
   UINT8                       TxeUmaEnable;                  /* Offset 0x004F */
-  UINT8                       UnusedUpdSpace1[160];          /* Offset 0x0050 */
+  UINT8                       PcdOsSelection;                /* Offset 0x0050 */
+  UINT8                       PcdEMMC45DDR50Enabled;         /* Offset 0x0051 */
+  UINT8                       PcdEMMC45HS200Enabled;         /* Offset 0x0052 */
+  UINT8                       PcdEMMC45RetuneTimerValue;     /* Offset 0x0053 */
+  UINT8                       PcdEnableIgd;                  /* Offset 0x0054 */
+  UINT8                       UnusedUpdSpace1[155];          /* Offset 0x0055 */
   MEMORY_DOWN_DATA            PcdMemoryParameters;           /* Offset 0x00F0 */
   UINT16                      PcdRegionTerminator;           /* Offset 0x0100 */
 } UPD_DATA_REGION;