sb/intel/lynxpoint: Drop `config_t` typedef

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I550198aae22fbe39f4b461332a10de82c78cd191
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57498
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 7 insertions, 12 deletions

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 01fff14529..f3c08d885f 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -24,8 +24,6 @@
 
 #define NMI_OFF	0
 
-typedef struct southbridge_intel_lynxpoint_config config_t;
-
 /**
  * Set miscellanous static southbridge features.
  *
@@ -146,7 +144,8 @@ static void pch_pirq_init(struct device *dev)
 	}
 }
 
-static void pch_gpi_routing(struct device *dev, config_t *config)
+static void pch_gpi_routing(struct device *dev,
+			    struct southbridge_intel_lynxpoint_config *config)
 {
 	u32 reg32 = 0;
 
@@ -246,7 +245,7 @@ static void pch_power_options(struct device *dev)
 	pci_write_config16(dev, GEN_PMCON_1, reg16);
 
 	if (dev->chip_info) {
-		config_t *config = dev->chip_info;
+		struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 
 		/*
 		 * Set the board's GPI routing on LynxPoint-H.
@@ -723,7 +722,7 @@ static void pch_lpc_add_io_resources(struct device *dev)
 
 	/* LPC Generic IO Decode range. */
 	if (dev->chip_info) {
-		config_t *config = dev->chip_info;
+		struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 		pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
 		pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
 		pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 1b69b8099f..c90c096a85 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -17,8 +17,6 @@
 #define SATA_PORT_MASK	0x3f
 #endif
 
-typedef struct southbridge_intel_lynxpoint_config config_t;
-
 static inline u32 sir_read(struct device *dev, int idx)
 {
 	pci_write_config32(dev, SATA_SIRI, idx);
@@ -46,7 +44,7 @@ static void sata_init(struct device *dev)
 	u32 *abar;
 
 	/* Get the chip configuration */
-	config_t *config = dev->chip_info;
+	struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 
 	printk(BIOS_DEBUG, "SATA: Initializing...\n");
 
@@ -199,7 +197,7 @@ static void sata_init(struct device *dev)
 static void sata_enable(struct device *dev)
 {
 	/* Get the chip configuration */
-	config_t *config = dev->chip_info;
+	struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 
 	if (!config)
 		return;
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index ce851a3009..f049ee2af3 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -11,8 +11,6 @@
 #include "iobp.h"
 #include "pch.h"
 
-typedef struct southbridge_intel_lynxpoint_config config_t;
-
 #ifdef __SIMPLE_DEVICE__
 static u8 *usb_xhci_mem_base(pci_devfn_t dev)
 #else
@@ -277,7 +275,7 @@ static void usb_xhci_init(struct device *dev)
 {
 	u32 reg32;
 	u8 *mem_base = usb_xhci_mem_base(dev);
-	config_t *config = dev->chip_info;
+	struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 
 	/* D20:F0:74h[1:0] = 00b (set D0 state) */
 	pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0);