kontron/ktqm77: New board

Change-Id: Ife1c0a8597c2de04773899cdd87af6b6c630906a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3392
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

19 files changed, 2239 insertions, 0 deletions

diff --git a/src/mainboard/kontron/Kconfig b/src/mainboard/kontron/Kconfig
index 5d64476b7f..f4ab89fa00 100644
--- a/src/mainboard/kontron/Kconfig
+++ b/src/mainboard/kontron/Kconfig
@@ -7,11 +7,14 @@ config BOARD_KONTRON_986LCD_M
 	bool "986LCD-M/mITX"
 config BOARD_KONTRON_KT690
 	bool "KT690/mITX"
+config BOARD_KONTRON_KTQM77
+	bool "KTQM77/mITX"
 
 endchoice
 
 source "src/mainboard/kontron/986lcd-m/Kconfig"
 source "src/mainboard/kontron/kt690/Kconfig"
+source "src/mainboard/kontron/ktqm77/Kconfig"
 
 config MAINBOARD_VENDOR
 	string
diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig
new file mode 100644
index 0000000000..dafc95981a
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/Kconfig
@@ -0,0 +1,87 @@
+if BOARD_KONTRON_KTQM77
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_RPGA989
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select SOUTHBRIDGE_INTEL_C216
+	select SUPERIO_WINBOND_W83627DHG
+	select EC_KONTRON_IT8516E
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select MMCONF_SUPPORT
+	select HAVE_SMI_HANDLER
+	select GFXUMA
+	select EXTERNAL_MRC_BLOB
+	select EARLY_CBMEM_INIT
+	select ENABLE_VMX
+	select HAVE_MRC
+
+config MRC_FILE
+	string
+	default "3rdparty/northbridge/intel/sandybridge/systemagent-ivybridge.bin"
+
+config MAINBOARD_DIR
+	string
+	default kontron/ktqm77
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "KTQM77/mITX"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 8
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0166.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x0000 # TODO
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x0000 # TODO
+
+config MAINBOARD_VENDOR
+	string
+	default "Kontron"
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config HAVE_ME_BIN
+	bool
+	default n
+
+config HAVE_GBE_BIN
+	bool
+	default n
+
+config IFD_BIOS_SECTION
+	string
+	default "0x00580000:0x007fffff"
+
+config IFD_ME_SECTION
+	string
+	default "0x00003000:0x0057ffff"
+
+config IFD_GBE_SECTION
+	string
+	default "0x00001000:0x00002fff"
+
+endif # BOARD_KONTRON_KTQM77
diff --git a/src/mainboard/kontron/ktqm77/acpi/ec.asl b/src/mainboard/kontron/ktqm77/acpi/ec.asl
new file mode 100644
index 0000000000..7925e0db67
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/ec.asl
@@ -0,0 +1,7 @@
+#define IT8516E_EC_DEV		EC0
+#define SUPERIO_PNP_BASE	0x20e
+#define IT8516E_FIRST_DATA	0x62
+#define IT8516E_FIRST_SC	0x66
+#define IT8516E_SECOND_DATA	0x20c
+#define IT8516E_SECOND_SC	0x20d
+#include <ec/kontron/it8516e/acpi/ec.asl>
diff --git a/src/mainboard/kontron/ktqm77/acpi/mainboard.asl b/src/mainboard/kontron/ktqm77/acpi/mainboard.asl
new file mode 100644
index 0000000000..10b1c1108a
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/mainboard.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+	Device (PWRB)
+	{
+		Name (_HID, EisaId("PNP0C0C"))
+	}
+}
diff --git a/src/mainboard/kontron/ktqm77/acpi/platform.asl b/src/mainboard/kontron/ktqm77/acpi/platform.asl
new file mode 100644
index 0000000000..ff6d94d05a
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/platform.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
diff --git a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000000..b93aa96569
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Ivybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// LPC devices			0:1f.x
+							   //  D31IP_TTIP  THRT   INTC -> PIRQC
+			Package() { 0x001fffff, 2, 0, 18 },//  D31IP_SMIP  SMBUS  INTC -> PIRQC
+			Package() { 0x001fffff, 1, 0, 19 },//  D31IP_SIP   SATA   INTB -> PIRQD (MSI)
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 23 },//  D29IP_E1P   EHCI1  INTA -> PIRQH
+			// PCIe Root Ports		0:1c.x
+							   //  D28IP_P8IP  Slot?  INTD -> PIRQD
+			Package() { 0x001cffff, 3, 0, 19 },//  D28IP_P4IP  ETH2   INTD -> PIRQD (MSI)
+							   //  D28IP_P7IP  PCIEx1 INTC -> PIRQC
+			Package() { 0x001cffff, 2, 0, 18 },//  D28IP_P3IP  ETH1   INTC -> PIRQC (MSI)
+							   //  D28IP_P6IP  1394   INTB -> PIRQB (MSI)
+			Package() { 0x001cffff, 1, 0, 17 },//  D28IP_P2IP  Slot?  INTB -> PIRQB
+							   //  D28IP_P5IP  GbEPHY INTA -> PIRQA
+			Package() { 0x001cffff, 0, 0, 16 },//  D28IP_P1IP  Slot?  INTA -> PIRQA
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },//  D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 16 },//  D26IP_E2P   EHCI2  INTA -> PIRQA
+			// ETH0				0:19.0
+			Package() { 0x0019ffff, 0, 0, 20 },//  D25IP_LIP   ETH0   INTA -> PIRQE (MSI)
+			// xHCI				0:14.0
+			Package() { 0x0014ffff, 0, 0, 16 },//  D20IP_XHCIIP xHCI  INTA -> PIRQA (MSI)
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
+			// PCIe PEG x16			0:1.0
+			Package() { 0x0001ffff, 3, 0, 19 },//              PEGx16 INTD -> PIRQD
+			Package() { 0x0001ffff, 2, 0, 18 },//              PEGx16 INTC -> PIRQC
+			Package() { 0x0001ffff, 1, 0, 17 },//              PEGx16 INTB -> PIRQB
+			Package() { 0x0001ffff, 0, 0, 16 },//              PEGx16 INTA -> PIRQA
+		})
+	} Else {
+		Return (Package() {
+			// LPC devices			0:1f.x
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// ETH0				0:19.0
+			Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// xHCI				0:14.0
+			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe PEG x16			0:1.0
+			Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/kontron/ktqm77/acpi/superio.asl b/src/mainboard/kontron/ktqm77/acpi/superio.asl
new file mode 100644
index 0000000000..1ed4c931fc
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/superio.asl
@@ -0,0 +1,12 @@
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef W83627DHG_SHOW_UARTA
+#undef W83627DHG_SHOW_UARTB
+#undef W83627DHG_SHOW_KBC
+#undef W83627DHG_SHOW_PS2M
+#undef W83627DHG_SHOW_HWMON
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+#define W83627DHG_SHOW_UARTA	1
+#define W83627DHG_SHOW_UARTB	1
+#include <superio/winbond/w83627dhg/acpi/superio.asl>
diff --git a/src/mainboard/kontron/ktqm77/acpi/thermal.asl b/src/mainboard/kontron/ktqm77/acpi/thermal.asl
new file mode 100644
index 0000000000..093151a82e
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/thermal.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Return CPU Temperature from EC
+			Return (\_SB.PCI0.LPCB.EC0.PM1.CTK ())
+		}
+
+// The EC does all fan control. There is no Active Cooling Fan control (_ACx).
+	}
+}
diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c
new file mode 100644
index 0000000000..ed6d35775a
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi_tables.c
@@ -0,0 +1,254 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+	/* EC handles all thermal and fan control on Butterfly. */
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* CBMEM TOC */
+	gnvs->cmem = (u32)get_cbmem_toc();
+
+	/* IGD Displays */
+	gnvs->ndid = 0;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+
+	acpi_update_thermal_table(gnvs);
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+					const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+			     "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			acpi_save_gnvs(current);
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* And tell SMI about it */
+	smm_setup_structures((void *)current, NULL, NULL);
+
+	current += sizeof(global_nvs_t);
+	ALIGN_CURRENT;
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout
new file mode 100644
index 0000000000..295ecd3a1d
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/cmos.layout
@@ -0,0 +1,155 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+416        424       s       0        boot_devices
+840          8       h       0        boot_default
+848          1       e       9        cmos_defaults_loaded
+#849          7       r       0        unused
+
+# coreboot config options: mainboard specific options
+856          2       e       8        fan1_mode
+858          2       r       0        fan1_reserved
+860          2       e       8        fan2_mode
+862          2       r       0        fan2_reserved
+864         16       h       0        fan1_target
+880         16       h       0        fan2_target
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+960         16        r       0        mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+8     0     Auto
+8     1     PWM
+8     2     Speed
+8     3     Thermal
+9     0     No
+9     1     Yes
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
new file mode 100644
index 0000000000..65c03c48d9
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -0,0 +1,163 @@
+chip northbridge/intel/sandybridge
+
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_206ax
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+
+			# Coordinate with HW_ALL
+			register "pstate_coord_type" = "0xfe" # TODO: This is never read.
+
+			register "c1_acpower" = "1"	# ACPI(C1) = MWAIT(C1)
+			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C3)
+			register "c3_acpower" = "0"	# ACPI(C3) = MWAIT(C7)
+
+			register "c1_battery" = "1"	# ACPI(C1) = MWAIT(C1)
+			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C3)
+			register "c3_battery" = "0"	# ACPI(C3) = MWAIT(C7)
+		end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 01.0 on end # PCIe Bridge x16
+		device pci 02.0 on end # vga controller
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8b"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8b"
+			register "pirqe_routing" = "0x8b"
+			register "pirqf_routing" = "0x8b"
+			register "pirqg_routing" = "0x8b"
+			register "pirqh_routing" = "0x8b"
+
+			register "ide_legacy_combined" = "0x0" # TODO: Does nothing since generations, remove from sb code?
+			register "sata_ahci" = "0x1"
+			# Enable all SATA ports 0-5
+			register "sata_port_map" = "0x3f"
+			# Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
+			register "sata_interface_speed_support" = "0x3"
+
+			# TODO: Enable generic LPC decodes...
+			register "gen1_dec" = "0x001c02e1"
+			#register "gen2_dec" = "0x00000000"
+			#register "gen3_dec" = "0x00000000"
+			#register "gen4_dec" = "0x00000000"
+
+			# Disable root port coalescing
+			register "pcie_port_coalesce" = "0"
+
+			device pci 14.0 on end # USB 3.0 Controller
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 on end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2
+			device pci 1b.0 on end # High Definition Audio
+
+			# Disabling 1c.0 might break IRQ settings as it enables port coalescing
+			# There are two mini PCIe x1 sockets, so one PCIe port is unrouted
+			device pci 1c.0 on end # PCIe Port #1 mini PCIe x1?
+			device pci 1c.1 on end # PCIe Port #2 mini PCIe x1?
+			device pci 1c.2 on end # PCIe Port #3 second Ethernet NIC
+			device pci 1c.3 on end # PCIe Port #4 third Ethernet NIC
+			device pci 1c.4 on end # PCIe Port #5 first Ethernet PHY
+			device pci 1c.5 on end # PCIe Port #6 FireWire
+			device pci 1c.6 on end # PCIe Port #7 PCIe x1
+			device pci 1c.7 on end # PCIe Port #8 mini PCIe x1?
+
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on #LPC bridge
+				chip superio/winbond/w83627dhg
+					device pnp 2e.0 off #  Floppy
+					end
+					device pnp 2e.1 off #  Parallel Port
+					end
+					device pnp 2e.2 on #  Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on #  Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.5 off #  Keyboard
+					end
+					device pnp 2e.6 off #  SPI
+					end
+					device pnp 2e.307 off #  GPIO 1
+					end
+					device pnp 2e.8 off #  WDTO#, PLED
+					end
+					device pnp 2e.009 on #  GPIO2 -- original firmware sets this on
+					end
+					device pnp 2e.109 on #  GPIO3 -- original firmware sets this on
+					end
+					device pnp 2e.209 off #  GPIO4
+					end
+					device pnp 2e.309 off #  GPIO5
+					end
+					device pnp 2e.a off #  ACPI
+					end
+					device pnp 2e.b off # HWM
+					end
+					device pnp 2e.c off # PECI, SST
+					end
+				end	#superio/winbond/w83627dhg
+				chip ec/kontron/it8516e
+					# Set CPU Fan to 50°C, System Fan to 75%
+					register "default_fan_mode" = "{ IT8516E_MODE_THERMAL, IT8516E_MODE_PWM }"
+					register "default_fan_target" = "{ 50, 75 }"
+
+					# TODO: Check status when Linux runs
+					device pnp 20e.1 on #  Com3
+						io 0x60 = 0x03e8
+						irq 0x70 = 4
+					end
+					device pnp 20e.2 on #  Com4
+						io 0x60 = 0x02e8
+						irq 0x70 = 3
+					end
+					device pnp 20e.4 off #  System Wakeup
+					end
+					device pnp 20e.5 on #  Mouse
+						irq 0x70 = 12
+					end
+					device pnp 20e.6 on #  Keyboard
+						io 0x60 = 0x0060
+						io 0x62 = 0x0064
+						irq 0x70 = 1
+					end
+					device pnp 20e.f off #  Shared Memory
+					end
+					device pnp 20e.10 off #  BRAM / RTC
+					end
+					device pnp 20e.11 on #  PM channel 1
+						io 0x60 = 0x0062
+						io 0x62 = 0x0066
+						irq 0x70 = 0
+					end
+					device pnp 20e.12 on #  PM channel 2
+						io 0x60 = 0x020c
+						io 0x62 = 0x020d
+						irq 0x70 = 0
+					end
+					device pnp 20e.17 off #  PM channel 3
+					end
+				end	#ec/kontron/it8516e
+				# TODO: TPM on 4e
+			end # LPC bridge
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl
new file mode 100644
index 0000000000..3af7a0e0b6
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/dsdt.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include "acpi/mainboard.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	#include "acpi/thermal.asl"
+
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/kontron/ktqm77/fadt.c b/src/mainboard/kontron/ktqm77/fadt.c
new file mode 100644
index 0000000000..b8da1be0a9
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/fadt.c
@@ -0,0 +1,169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT		0xb2
+#define CST_CONTROL	0x85
+#define PST_CONTROL	0x80
+#define ACPI_DISABLE	0x1e
+#define ACPI_ENABLE	0xe1
+#define GNVS_UPDATE	0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+								0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = ACPI_ENABLE;
+	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 16;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 101;  /* c2 not supported */
+	fadt->p_lvl3_lat = 87;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+	fadt->flags = ACPI_FADT_WBINVD |
+			ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_RESET_REGISTER |
+			ACPI_FADT_SEALED_CASE |
+			ACPI_FADT_S4_RTC_WAKE |
+			ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/kontron/ktqm77/gpio.h b/src/mainboard/kontron/ktqm77/gpio.h
new file mode 100644
index 0000000000..f99e02881b
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/gpio.h
@@ -0,0 +1,303 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef KTQM77_GPIO_H
+#define KTQM77_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+/*
+ * TODO: Investigate somehow... Current values are taken from a running
+ *       system with vendor supplied firmware.
+ */
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0  = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio1  = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio2  = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio3  = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio4  = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio5  = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio6  = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio7  = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio8  = GPIO_MODE_GPIO,   /* Unknown Output LOW*/
+	.gpio9  = GPIO_MODE_NATIVE, /* Native - OC5# pin */
+	.gpio10 = GPIO_MODE_NATIVE, /* Native - OC6# pin */
+	.gpio11 = GPIO_MODE_NATIVE, /* Native - SMBALERT# pin */
+	.gpio12 = GPIO_MODE_NATIVE, /* Native - LAN_PHY_PWR_CTRL */
+	.gpio13 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio14 = GPIO_MODE_NATIVE, /* Native - OC7# pin */
+	.gpio15 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
+	.gpio16 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio17 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
+	.gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin */
+	.gpio19 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
+	.gpio20 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio21 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio22 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio23 = GPIO_MODE_NATIVE, /* Native - LDRQ1# pin */
+	.gpio24 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
+	.gpio25 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio26 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ4# pin */
+	.gpio27 = GPIO_MODE_GPIO,   /* Unknown Input */ /* Vendor supplied DSDT sets this conditionally
+							   when going to suspend (S3, S4, S5). */
+	.gpio28 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
+	.gpio29 = GPIO_MODE_NATIVE,   /* Native - SLP_LAN# pin, forced by soft strap */
+	.gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# pin */
+	.gpio31 = GPIO_MODE_NATIVE  /* Native - ACPRESENT */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0  = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio1  = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio2  = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio3  = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio4  = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio5  = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio6  = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio7  = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio8  = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio9  = GPIO_DIR_INPUT,  /* Native */
+	.gpio10 = GPIO_DIR_INPUT,  /* Native */
+	.gpio11 = GPIO_DIR_INPUT,  /* Native */
+	.gpio12 = GPIO_DIR_INPUT,  /* Native */
+	.gpio13 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio14 = GPIO_DIR_INPUT,  /* Native */
+	.gpio15 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio16 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio17 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio18 = GPIO_DIR_INPUT,  /* Native */
+	.gpio19 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+	.gpio20 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio21 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio22 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio23 = GPIO_DIR_INPUT,  /* Native */
+	.gpio24 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+	.gpio25 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio26 = GPIO_DIR_INPUT,  /* Native */
+	.gpio27 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio28 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+	.gpio29 = GPIO_DIR_INPUT,  /* Native */
+	.gpio30 = GPIO_DIR_INPUT,  /* Native */
+	.gpio31 = GPIO_DIR_INPUT,  /* Native */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0  = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio1  = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio2  = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio3  = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio4  = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio5  = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio6  = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio7  = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio8  = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio9  = GPIO_LEVEL_LOW,  /* Native */
+	.gpio10 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio11 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio12 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio13 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio14 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio15 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio16 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio17 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio18 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio19 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+	.gpio20 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio21 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio22 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio23 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio24 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+	.gpio25 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio26 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio27 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio28 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+	.gpio29 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio30 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio31 = GPIO_LEVEL_LOW,  /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE, /* Native - CLKRUN# pin */
+	.gpio33 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
+	.gpio34 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio35 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
+	.gpio36 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio37 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio38 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio39 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio40 = GPIO_MODE_NATIVE, /* Native - OC1# pin */
+	.gpio41 = GPIO_MODE_NATIVE, /* Native - OC2# pin */
+	.gpio42 = GPIO_MODE_NATIVE, /* Native - OC3# pin */
+	.gpio43 = GPIO_MODE_NATIVE, /* Native - OC4# pin */
+	.gpio44 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ5# pin */
+	.gpio45 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ6# pin */
+	.gpio46 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ7# pin */
+	.gpio47 = GPIO_MODE_NATIVE, /* Native - PEG_A_CLKRQ# pin */
+	.gpio48 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio49 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio50 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
+	.gpio51 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio52 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
+	.gpio53 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
+	.gpio54 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
+	.gpio55 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio56 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio57 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio58 = GPIO_MODE_NATIVE, /* Native - SML1CLK */
+	.gpio59 = GPIO_MODE_NATIVE, /* Native - OC0# pin */
+	.gpio60 = GPIO_MODE_GPIO,   /* Unknown Output HIGH */
+	.gpio61 = GPIO_MODE_NATIVE, /* Native - SUS_STAT# pin*/
+	.gpio62 = GPIO_MODE_NATIVE, /* Native - SUSCLK */
+	.gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5# */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,  /* Native */
+	.gpio33 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio34 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio35 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+	.gpio36 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio37 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio38 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio39 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio40 = GPIO_DIR_INPUT,  /* Native */
+	.gpio41 = GPIO_DIR_INPUT,  /* Native */
+	.gpio42 = GPIO_DIR_INPUT,  /* Native */
+	.gpio43 = GPIO_DIR_INPUT,  /* Native */
+	.gpio44 = GPIO_DIR_INPUT,  /* Native */
+	.gpio45 = GPIO_DIR_INPUT,  /* Native */
+	.gpio46 = GPIO_DIR_INPUT,  /* Native */
+	.gpio47 = GPIO_DIR_INPUT,  /* Native */
+	.gpio48 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio49 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio50 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio51 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio52 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+	.gpio53 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+	.gpio54 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio55 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio56 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio57 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio58 = GPIO_DIR_INPUT,  /* Native */
+	.gpio59 = GPIO_DIR_INPUT,  /* Native */
+	.gpio60 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+	.gpio61 = GPIO_DIR_INPUT,  /* Native */
+	.gpio62 = GPIO_DIR_INPUT,  /* Native */
+	.gpio63 = GPIO_DIR_INPUT,  /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio33 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio34 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio35 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+	.gpio36 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio37 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio38 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio39 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio40 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio41 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio42 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio43 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio44 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio45 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio46 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio47 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio48 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio49 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio50 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio51 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio52 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+	.gpio53 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+	.gpio54 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio55 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio56 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio57 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio58 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio59 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio60 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+	.gpio61 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio62 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio63 = GPIO_LEVEL_LOW,  /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
+	.gpio65 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
+	.gpio66 = GPIO_MODE_GPIO,   /* Unknown Output LOW */
+	.gpio67 = GPIO_MODE_NATIVE, /* Native - CLKOUTFLEX3 */
+	.gpio68 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio69 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio70 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio71 = GPIO_MODE_GPIO,   /* Unknown Input */
+	.gpio72 = GPIO_MODE_NATIVE, /* Native - nothing on mobile */
+	.gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# pin */
+	.gpio74 = GPIO_MODE_NATIVE, /* Native - SML1ALERT#/PCHHOT# pin */
+	.gpio75 = GPIO_MODE_NATIVE, /* Native - SML1DATA */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio65 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+	.gpio67 = GPIO_DIR_INPUT,  /* Native */
+	.gpio68 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio69 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio70 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio71 = GPIO_DIR_INPUT,  /* Unknown Input */
+	.gpio72 = GPIO_DIR_INPUT,  /* Native */
+	.gpio73 = GPIO_DIR_INPUT,  /* Native */
+	.gpio74 = GPIO_DIR_INPUT,  /* Native */
+	.gpio75 = GPIO_DIR_INPUT,  /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio65 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio66 = GPIO_LEVEL_LOW,  /* Unknown Output LOW */
+	.gpio67 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio68 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio69 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio70 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio71 = GPIO_LEVEL_LOW,  /* Unknown Input */
+	.gpio72 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio73 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio74 = GPIO_LEVEL_LOW,  /* Native */
+	.gpio75 = GPIO_LEVEL_LOW,  /* Native */
+};
+
+const struct pch_gpio_map ktqm77_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+	},
+};
+#endif
diff --git a/src/mainboard/kontron/ktqm77/hda_verb.h b/src/mainboard/kontron/ktqm77/hda_verb.h
new file mode 100644
index 0000000000..53b3fc9f35
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/hda_verb.h
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012-2013 secunet Security Networks AG
+ * Copyright (C) 2013 Nico Huber <nico.h@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Pin widget configuration:
+ *
+ * Port-Con.  Location  Def.-Dev.  Con.-Type   Color    Misc  Def.-Aso.     Seq
+ *    31..30    29..24     23..20     19..16  15..12  11..00     07..04  03..00
+ */
+#define PIN_CFG(pin, val) \
+	(pin << 20) | ( 0x71c << 8) | (val & 0xff), \
+	(pin << 20) | ( 0x71d << 8) | ((val >> 8) & 0xff), \
+	(pin << 20) | ( 0x71e << 8) | ((val >> 16) & 0xff), \
+	(pin << 20) | ( 0x71f << 8) | ((val >> 24) & 0xff), \
+
+static const u32 mainboard_cim_verb_data[] = {
+	/* coreboot specific header */
+	0x11060397,	// Codec Vendor / Device ID: Via VT1708S
+	0x11060000,	// Subsystem ID
+	0x0000000c,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x11060000 */
+	0x00172000,
+	0x00172100,
+	0x00172206,
+	0x00172311,
+
+	/* Pin Widget Verb Table */
+
+	/*
+	 * NID 0x19 [Port A (SURR)]:
+	 * Jack     Internal    Speaker     N/A             Black
+	 */
+	PIN_CFG(0x19, 0x10101112)
+
+	/*
+	 * NID 0x1a [Port B (MIC1/2)]:
+	 * Jack     Rear        Mic In      1/8"            Pink
+	 */
+	PIN_CFG(0x1a, 0x01a19036)
+
+	/*
+	 * NID 0x1b [Port C (LINEIN)]:
+	 * Jack     Rear        Line In     1/8"            Blue
+	 */
+	PIN_CFG(0x1b, 0x0181303e)
+
+	/*
+	 * NID 0x1c [Port D (Front)]:
+	 * Jack     Rear        Line Out    1/8"            Green
+	 */
+	PIN_CFG(0x1c, 0x01014010)
+
+	/*
+	 * NID 0x1d [Port E (Front HP/MIC)]:
+	 * Jack     Front       HP Out      1/8"            Green
+	 */
+	PIN_CFG(0x1d, 0x022141f0)
+
+	/*
+	 * NID 0x1e [Port F (Front HP/MIC)]:
+	 * Jack     Front       Mic In      1/8"            Pink
+	 */
+	PIN_CFG(0x1e, 0x02a19138)
+
+	/*
+	 * NID 0x1f [CD]:
+	 * Jack     Int.(ATAPI) CD          ATAPI internal  Black
+	 */
+	PIN_CFG(0x1f, 0x19331137)
+
+	/*
+	 * NID 0x20 [N/A]:
+	 * Jack     Rear        S/PDIF Out  RCA             Unknown
+	 */
+	PIN_CFG(0x20, 0x014401f0)
+
+	/*
+	 * NID 0x21 [N/A]:
+	 * None     Internal    S/PDIF Out  Other Digital   Unknown
+	 */
+	PIN_CFG(0x21, 0x504600f0)
+
+	/*
+	 * NID 0x22 [Port G (C/LFE)]:
+	 * Jack     Internal    Speaker     Unknown         Orange
+	 */
+	PIN_CFG(0x22, 0x10106111)
+
+	/*
+	 * NID 0x23 [Port H (SSL/SSR)]:
+	 * Jack     Internal    Speaker     Unknown         Grey
+	 */
+	PIN_CFG(0x23, 0x10102114)
+
+
+	/* coreboot specific header */
+	0x80862806,	// Codec Vendor / Device ID: Intel PantherPoint HDMI
+	0x80860101,	// Subsystem ID
+	0x00000004,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+	0x00172001,
+	0x00172101,
+	0x00172286,
+	0x00172380,
+
+	/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+	0x30571c10,
+	0x30571d00,
+	0x30571e56,
+	0x30571f58,
+
+	/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+	0x30671c20,
+	0x30671d00,
+	0x30671e56,
+	0x30671f18,
+
+	/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+	0x30771c30,
+	0x30771d00,
+	0x30771e56,
+	0x30771f18
+};
diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c
new file mode 100644
index 0000000000..454976cfab
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/mainboard.c
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void mainboard_suspend_resume(void)
+{
+	/* Call SMM finalize() handlers before resume */
+	outb(0xcb, 0xb2);
+}
+
+#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+	int res = 0;
+
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+	switch(X86_EAX & 0xffff) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		X86_EAX &= 0xffff0000;
+		X86_EAX |= 0x005f;
+		X86_ECX &= 0xffffff00;
+		X86_ECX |= 0x00;	/* Use video bios default */
+		res = 1;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP)
+		 *  bit 2 = EFP
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP)
+		 *  bit 6 = EFP2
+		 *  bit 7 = LFP2
+		 */
+		X86_EAX &= 0xffff0000;
+		X86_EAX |= 0x005f;
+		X86_ECX &= 0xffff0000;
+		X86_ECX |= 0x0000;	/* Use video bios default */
+		res = 1;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SDVO-LVDS, LFP driven by SDVO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		X86_EAX &= 0xffff0000;
+		X86_EAX |= 0x005f;
+		X86_ECX &= 0xffff0000;
+		X86_ECX |= 0x0000; /* TODO: Make this configurable in NVRAM? */
+		res = 1;
+		break;
+	case 0x5f70:
+		switch ((X86_ECX >> 8) & 0xff) {
+		case 0:
+			/* Get Mux */
+			X86_EAX &= 0xffff0000;
+			X86_EAX |= 0x005f;
+			X86_ECX &= 0xffff0000;
+			X86_ECX |= 0x0000;
+			res = 1;
+			break;
+		case 1:
+			/* Set Mux */
+			X86_EAX &= 0xffff0000;
+			X86_EAX |= 0x005f;
+			X86_ECX &= 0xffff0000;
+			X86_ECX |= 0x0000;
+			res = 1;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			X86_EAX &= 0xffff0000;
+			X86_EAX |= 0x005f;
+			X86_ECX &= 0xffff0000;
+			X86_ECX |= 0x0000;
+			res = 1;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				((X86_ECX >> 8) & 0xff));
+			return 1;
+		}
+		break;
+
+        default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+		       X86_EAX & 0xffff);
+		break;
+	}
+	return res;
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+	cim_verb_data = mainboard_cim_verb_data;
+	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	/* Install custom int15 handler for VGA OPROM */
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+	verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
new file mode 100644
index 0000000000..79fafe0273
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -0,0 +1,350 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+
+static void pch_enable_lpc(void)
+{
+	/* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070);
+
+	/* Enable KBC on 0x06/0x64 (KBC),
+	 *        EC on 0x62/0x66 (MC),
+	 *        EC on 0x20c-0x20f (GAMEH),
+	 *        Super I/O on 0x2e/0x2f (CNF1),
+	 *	  COM1/COM3 decode ranges. */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN,
+			   KBC_LPC_EN | MC_LPC_EN |
+			   CNF1_LPC_EN | GAMEH_LPC_EN |
+			   COMA_LPC_EN | COMB_LPC_EN);
+}
+
+static void rcba_config(void)
+{
+	u32 reg32;
+
+	/*
+	 * D31IP_TTIP   THRT   INTC -> PIRQC
+	 * D31IP_SIP2   SATA2  NOINT
+	 * D31IP_SMIP   SMBUS  INTC -> PIRQC
+	 * D31IP_SIP    SATA   INTB -> PIRQD (MSI)
+	 * D29IP_E1P    EHCI1  INTA -> PIRQH
+	 * D28IP_P8IP   Slot?  INTD -> PIRQD
+	 * D28IP_P7IP   PCIEx1 INTC -> PIRQC
+	 * D28IP_P6IP   1394   INTB -> PIRQB (MSI)
+	 * D28IP_P5IP   GbEPHY INTA -> PIRQA
+	 * D28IP_P4IP   ETH2   INTD -> PIRQD (MSI)
+	 * D28IP_P3IP   ETH1   INTC -> PIRQC (MSI)
+	 * D28IP_P2IP   Slot?  INTB -> PIRQB
+	 * D28IP_P1IP   Slot?  INTA -> PIRQA
+	 * D27IP_ZIP    HDA    INTA -> PIRQG (MSI)
+	 * D26IP_E2P    EHCI2  INTA -> PIRQA
+	 * D25IP_LIP    ETH0   INTA -> PIRQE (MSI)
+	 * D22IP_KTIP   MEI    NOINT
+	 * D22IP_IDERIP MEI    NOINT
+	 * D22IP_MEI2IP MEI    NOINT
+	 * D22IP_MEI1IP MEI    NOINT
+	 * D20IP_XHCIIP XHCI   INTA -> PIRQA (MSI)
+	 *              GFX    INTA -> PIRQA (MSI)
+	 *              PEGx16 INTA -> PIRQA
+	 *                     INTB -> PIRQB
+	 *                     INTC -> PIRQC
+	 *                     INTD -> PIRQD
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+			(INTC << D31IP_SMIP) | (INTB << D31IP_SIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+			(INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) |
+			(INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) |
+			(INTC << D28IP_P7IP) | (INTD << D28IP_P8IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (INTA << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+	RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA);
+	DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC);
+	DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD);
+	DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH);
+	DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB);
+	DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
+
+	/* Disable unused devices (board specific) */
+	reg32 = RCBA32(FD);
+	reg32 |= PCH_DISABLE_ALWAYS;
+	/* Disable PCI bridge so MRC does not probe this bus */
+	reg32 |= PCH_DISABLE_P2P;
+	RCBA32(FD) = reg32;
+}
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0x87, port);
+	outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0xaa, port);
+}
+
+static void superio_gpio_config(void)
+{
+	device_t dev = PNP_DEV(0x2e, 0x9);
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	/* Values can only be changed, when devices are enabled. */
+	pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */
+	pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */
+	pnp_write_config(dev, 0xe4, 0x22); /* GPIO2 bits 1, 5 are 1 */
+	pnp_exit_ext_func_mode(dev);
+}
+
+void main(unsigned long bist)
+{
+	int boot_mode = 0;
+	int cbmem_was_initted;
+	u32 pm1_cnt;
+	u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	tsc_t start_romstage_time;
+	tsc_t before_dram_time;
+	tsc_t after_dram_time;
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+#endif
+	struct pei_data pei_data = {
+		pei_version: PEI_VERSION,
+		mchbar: DEFAULT_MCHBAR,
+		dmibar: DEFAULT_DMIBAR,
+		epbar: DEFAULT_EPBAR,
+		pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+		smbusbar: SMBUS_IO_BASE,
+		wdbbar: 0x4000000,
+		wdbsize: 0x1000,
+		hpet_address: CONFIG_HPET_ADDRESS,
+		rcba: DEFAULT_RCBABASE,
+		pmbase: DEFAULT_PMBASE,
+		gpiobase: DEFAULT_GPIOBASE,
+		thermalbase: 0xfed08000,
+		system_type: 0, // 0 Mobile, 1 Desktop/Server
+		tseg_size: CONFIG_SMM_TSEG_SIZE,
+		spd_addresses: { 0xA0, 0x00,0xA4,0x00 },
+		ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+		ec_present: 1,
+		gbe_enable: 1,
+		ddr3lv_support: 0,
+		// 0 = leave channel enabled
+		// 1 = disable dimm 0 on channel
+		// 2 = disable dimm 1 on channel
+		// 3 = disable dimm 0+1 on channel
+		dimm_channel0_disabled: 2,
+		dimm_channel1_disabled: 2,
+		max_ddr3_freq: 1600,
+		usb_port_config: {
+			 /* enabled   usb oc pin    length */
+			{ 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */
+			{ 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */
+			{ 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */
+			{ 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */
+			{ 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */
+			{ 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */
+			{ 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */
+			{ 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */
+			{ 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */
+			{ 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */
+			{ 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */
+			{ 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */
+			{ 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */
+			{ 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */
+		},
+		usb3: {
+			mode:			3,	/* Smart Auto? */
+			hs_port_switch_mask:	0xf,	/* All four ports. */
+			preboot_support:	1,	/* preOS driver? */
+			xhci_streams:		1,	/* Enable. */
+		},
+		pcie_init: 1,
+	};
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	start_romstage_time = rdtsc();
+#endif
+
+	if (bist == 0)
+		enable_lapic();
+
+	pch_enable_lpc();
+
+	/* Enable GPIOs */
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+	setup_pch_gpios(&ktqm77_gpio_map);
+	superio_gpio_config();
+
+	/* Initialize console device(s) */
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected\n");
+		boot_mode = 1;
+
+		/* System is not happy after keyboard reset... */
+		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+		outb(0x6, 0xcf9);
+		hlt();
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+	/* Enable PEG10 (1x16) */
+	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
+			   pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) |
+			   DEVEN_PEG10);
+
+	/* Check PM1_STS[15] to see if we are waking from Sx */
+	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+	/* Read PM1_CNT[12:10] to determine which Sx state */
+	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	post_code(0x38);
+	/* Enable SPD ROMs and DDR-III DRAM */
+	enable_smbus();
+
+	/* Prepare USB controller early in S3 resume */
+	if (boot_mode == 2)
+		enable_usb_bar();
+
+	post_code(0x39);
+
+	post_code(0x3a);
+	pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = rdtsc();
+#endif
+	sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = rdtsc();
+#endif
+	post_code(0x3c);
+
+	rcba_config();
+	post_code(0x3d);
+
+	quick_ram_check();
+	post_code(0x3e);
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+	cbmem_was_initted = !cbmem_initialize();
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+
+	*(u32 *)CBMEM_BOOT_MODE = 0;
+	*(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+	if ((boot_mode == 2) && cbmem_was_initted) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+		if (resume_backup_memory) {
+			*(u32 *)CBMEM_BOOT_MODE = boot_mode;
+			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+		}
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	} else if (boot_mode == 2) {
+		/* Failed S3 resume, reset to come up cleanly */
+		outb(0x6, 0xcf9);
+		hlt();
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	}
+#endif
+	post_code(0x3f);
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+	/* Keep this the last thing this function does. */
+	cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/kontron/ktqm77/smihandler.c b/src/mainboard/kontron/ktqm77/smihandler.c
new file mode 100644
index 0000000000..fd95b93e1d
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/smihandler.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+	printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif);
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		smm_get_gnvs()->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+	printk(BIOS_DEBUG, "warn: unknown mainboard_smi_gpi: %x\n", gpi_sts);
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc);
+	switch (apmc) {
+	case APMC_FINALIZE:
+		printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+		if (mainboard_finalized) {
+			printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+			return 0;
+		}
+
+		intel_me_finalize_smm();
+		intel_pch_finalize_smm();
+		intel_sandybridge_finalize_smm();
+		intel_model_206ax_finalize_smm();
+
+		mainboard_finalized = 1;
+		break;
+	}
+	return 0;
+}
diff --git a/src/mainboard/kontron/ktqm77/thermal.h b/src/mainboard/kontron/ktqm77/thermal.h
new file mode 100644
index 0000000000..4716cef63b
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/thermal.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef KTQM77_THERMAL_H
+#define KTQM77_THERMAL_H
+
+/* Active Thermal and fans are controlled by the EC. */
+
+	/* Temperature which OS will shutdown at */
+	#define CRITICAL_TEMPERATURE	100
+
+	/* Temperature which OS will throttle CPU */
+	#define PASSIVE_TEMPERATURE	90
+
+#endif