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authorElyes Haouas <ehaouas@noos.fr>2022-12-04 09:16:07 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-12-06 15:06:27 +0000
commitee4646e70e08f21eb5ccdbcec8b46da22e171cbe (patch)
tree55027a332e5601bcc2094217c1948ab32726aee8
parenta5e04af48469148af7277dfc353585ea9068de1c (diff)
nb/intel/sandybridge: Use write32p()
Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/northbridge/intel/sandybridge/early_init.c8
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c10
2 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 7acc5af845..e35251359a 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -23,14 +23,14 @@ static void systemagent_vtd_init(void)
mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1);
/* Lock policies */
- write32((void *)(GFXVT_BASE + 0xff0), 0x80000000);
+ write32p(GFXVT_BASE + 0xff0, 0x80000000);
const struct device *const azalia = pcidev_on_root(0x1b, 0);
if (azalia && azalia->enabled) {
- write32((void *)(VTVC0_BASE + 0xff0), 0x20000000);
- write32((void *)(VTVC0_BASE + 0xff0), 0xa0000000);
+ write32p(VTVC0_BASE + 0xff0, 0x20000000);
+ write32p(VTVC0_BASE + 0xff0, 0xa0000000);
} else {
- write32((void *)(VTVC0_BASE + 0xff0), 0x80000000);
+ write32p(VTVC0_BASE + 0xff0, 0x80000000);
}
}
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 4e958150dd..b3f913efa7 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1513,7 +1513,7 @@ static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b)
for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + 4 * j;
- write32((void *)addr, j & 2 ? b : a);
+ write32p(addr, j & 2 ? b : a);
}
sfence();
@@ -1538,11 +1538,11 @@ static void fill_pattern1(ramctr_timing *ctrl, int channel)
for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + j * 4;
- write32((void *)addr, 0xffffffff);
+ write32p(addr, 0xffffffff);
}
for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + channel_step + j * 4;
- write32((void *)addr, 0);
+ write32p(addr, 0);
}
sfence();
@@ -1948,7 +1948,7 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno)
val = ~val;
addr = (1 << 26) + offset + i * step + j * 4;
- write32((void *)addr, val);
+ write32p(addr, val);
}
}
} else {
@@ -1956,7 +1956,7 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno)
for (j = 0; j < 16; j++) {
const u32 val = pattern[i][j];
addr = (1 << 26) + offset + i * step + j * 4;
- write32((void *)addr, val);
+ write32p(addr, val);
}
}
sfence();