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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-12 11:46:42 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-12-01 10:27:44 +0000 |
| commit | ea6a3b488c238f9b79ee3aeaedaf6b06e2dc4023 (patch) | |
| tree | a719a066ca89d73441d031821d99857ebfb06c75 | |
| parent | cdb26fd011285124a6ed5e6be6dddc806ca5b3a8 (diff) | |
util/autoport: Update devicetree generation
CPU nodes are now declared in a common chipset.cb.
TESTED: generates a proper devicetree for x220 based on logs.
Change-Id: Ic1f2d3d611aa3979b846706b6f743f79a3c4e54d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69501
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | util/autoport/sandybridge.go | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 950286c6b6..a60018e955 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -36,34 +36,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { }, Children: []DevTreeNode{ { - Chip: "cpu_cluster", - Dev: 0, - Children: []DevTreeNode{ - { - Chip: "cpu/intel/model_206ax", - Comment: "FIXME: check all registers", - Registers: map[string]string{ - /* FIXME:XX hardcoded. */ - "acpi_c1": "1", - "acpi_c2": "3", - "acpi_c3": "5", - }, - Children: []DevTreeNode{ - { - Chip: "lapic", - Dev: 0, - }, - { - Chip: "lapic", - Dev: 0xacac, - Disabled: true, - }, - }, - }, - }, - }, - - { Chip: "domain", Dev: 0, PCIController: true, |