arch/x86,cpu/x86: Disable the %gs and %fs segments

The %fs and %gs segment are typically used to implement thread local
storage or cpu local storage. We don't currently use these in coreboot,
so there is no reason to map them. By setting the segment index to 0,
it disables the segment. If an instruction tries to read from one of
these segments an exception will be raised.

The end goal is to make cpu_info() use the %gs segment. This will remove
the stack alignment requirements and fix smm_do_relocation.

BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaa376e562acc6bd1dfffb7a23bdec82aa474c1d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

6 files changed, 12 insertions, 6 deletions

diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index b6375b1243..a4a7b28cbb 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -39,8 +39,9 @@ _start:
 	movl	%eax, %ds
 	movl	%eax, %es
 	movl	%eax, %ss
+	xor	%eax, %eax /* zero out the gs and fs segment index */
 	movl	%eax, %fs
-	movl	%eax, %gs
+	movl	%eax, %gs /* Will be used for cpu_info */
 #if ENV_X86_64
 	mov	$RAM_CODE_SEG64, %ecx
 	call	SetCodeSelector
diff --git a/src/cpu/x86/entry32.S b/src/cpu/x86/entry32.S
index ad4a7d032b..215d60182a 100644
--- a/src/cpu/x86/entry32.S
+++ b/src/cpu/x86/entry32.S
@@ -37,8 +37,9 @@ bootblock_protected_mode_entry:
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
+	xor	%ax, %ax /* zero out the gs and fs segment index */
 	movw	%ax, %fs
-	movw	%ax, %gs
+	movw	%ax, %gs /* Will be used for cpu_info */
 
 	/* Restore the BIST value to %eax */
 	movl	%ebp, %eax
diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index d36bc9a645..d2d43a2b5b 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -52,8 +52,9 @@ __ap_protected_start:
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
+	xor	%ax, %ax /* zero out the gs and fs segment index */
 	movw	%ax, %fs
-	movw	%ax, %gs
+	movw	%ax, %gs /* Will be used for cpu_info */
 
 	/* Load the Interrupt descriptor table */
 	lidt	idtarg
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index aa95461ae8..44b772bcc2 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -77,8 +77,9 @@ _start:
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
+	xor	%ax, %ax /* zero out the gs and fs segment index */
 	movw	%ax, %fs
-	movw	%ax, %gs
+	movw	%ax, %gs /* Will be used for cpu_info */
 
 	/* Load the Interrupt descriptor table */
 	mov	idt_ptr, %ebx
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
index 44ee7cb327..aa48ab69ec 100644
--- a/src/cpu/x86/smm/smm_stub.S
+++ b/src/cpu/x86/smm/smm_stub.S
@@ -93,8 +93,9 @@ smm_trampoline32:
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
+	xor	%ax, %ax /* zero out the gs and fs segment index */
 	movw	%ax, %fs
-	movw	%ax, %gs
+	movw	%ax, %gs /* Will be used for cpu_info */
 
 	/* The CPU number is calculated by reading the initial APIC id. Since
 	 * the OS can manipulate the APIC id use the non-changing cpuid result
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index b7805d06ab..19793a0f84 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -123,8 +123,9 @@ untampered_lapic:
 	movw	%ax, %ds
 	movw	%ax, %es
 	movw	%ax, %ss
+	xor	%ax, %ax /* zero out the gs and fs segment index */
 	movw	%ax, %fs
-	movw	%ax, %gs
+	movw	%ax, %gs /* Will be used for cpu_info */
 
 	/* FIXME: Incompatible with X2APIC_SUPPORT. */
 	/* Get this CPU's LAPIC ID */