mb/starlabs/labtop: Add LabTop Mk IV

Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/labtop-mk-iv-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

19 files changed, 1236 insertions, 6 deletions

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 02383c9ba2..c0442c479a 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -180,6 +180,7 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Star Labs Systems
 
+- [LabTop Mk IV](starlabs/labtop_cml.md)
 - [StarLite Mk III](starlabs/lite_glk.md)
 - [StarBook Mk V](starlabs/starbook_tgl.md)
 
diff --git a/Documentation/mainboard/starlabs/labtop_cml.md b/Documentation/mainboard/starlabs/labtop_cml.md
new file mode 100644
index 0000000000..2f70173bbb
--- /dev/null
+++ b/Documentation/mainboard/starlabs/labtop_cml.md
@@ -0,0 +1,87 @@
+# Star LabTop Mk IV
+
+## Specs
+
+- CPU (full processor specs available at https://ark.intel.com)
+    - Intel i7-10710U (Comet Lake)
+    - Intel i3-10110U (Comet Lake)
+- EC
+    - ITE IT8987E
+    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
+    - Battery
+    - Charger, using AC adapter or USB-C PD
+    - Suspend / resume
+- GPU
+    - Intel UHD Graphics 620
+    - GOP driver is recommended, VBT is provided
+    - eDP 13-inch 1920x1080 LCD
+    - HDMI video
+    - USB-C DisplayPort video
+- Memory
+    - 16GB on-board *1
+- Networking
+    - AX201 CNVi WiFi / Bluetooth soldered to PCBA
+- Sound
+    - Realtek ALC256
+    - Internal speakers
+    - Internal microphone
+    - Combined headphone / microphone 3.5-mm jack
+    - HDMI audio
+    - USB-C DisplayPort audio
+- Storage
+    - M.2 PCIe SSD
+    - RTS5129 MicroSD card reader
+- USB
+    - 1280x720 CCD camera
+    - USB 3.1 Gen 2 Type-C (left)
+    - USB 3.1 Gen 2 Type-A (left)
+    - USB 3.1 Gen 1 Type-A (right)
+
+[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c`
+
+## Building coreboot
+
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
+make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Model               | 25Q128JVSQ |
++---------------------+------------+
+| Size                | 16 MiB     |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig
index 6fe3446e93..1700fb1410 100644
--- a/src/mainboard/starlabs/labtop/Kconfig
+++ b/src/mainboard/starlabs/labtop/Kconfig
@@ -13,6 +13,18 @@ config BOARD_STARLABS_LABTOP_SERIES
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_STARLABS_LABTOP_CML
+	select BOARD_ROMSIZE_KB_16384
+	select BOARD_STARLABS_LABTOP_SERIES
+	select EC_STARLABS_NEED_ITE_BIN
+	select HAVE_INTEL_PTT
+	select HAVE_SPD_IN_CBFS
+	select MAINBOARD_HAS_CRB_TPM
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_TPM2
+	select SOC_INTEL_COMETLAKE_1
+	select SPI_FLASH_WINBOND
+
 config BOARD_STARLABS_STARBOOK_TGL
 	select BOARD_ROMSIZE_KB_16384
 	select BOARD_STARLABS_LABTOP_SERIES
@@ -53,7 +65,8 @@ config EC_STARLABS_ITE_BIN_PATH
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
 
 config EC_VARIANT_DIR
-	default "tgl" if !EC_STARLABS_MERLIN
+	default "cml" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_CML
+	default "tgl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_TGL
 
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
@@ -67,13 +80,16 @@ config MAINBOARD_DIR
 
 config MAINBOARD_FAMILY
 	string
-	default "B5"
+	default "L4" if BOARD_STARLABS_LABTOP_CML
+	default "B5" if BOARD_STARLABS_STARBOOK_TGL
 
 config MAINBOARD_PART_NUMBER
-	default "StarBook Mk V"
+	default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML
+	default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "StarBook"
+	default "StarBook" if BOARD_STARLABS_STARBOOK_TGL
+	default "LabTop"
 
 config ME_BIN_PATH
 	string
@@ -87,9 +103,10 @@ config UART_FOR_CONSOLE
 	default 2
 
 config USE_PM_ACPI_TIMER
-	default n
+	default n if BOARD_STARLABS_STARBOOK_TGL
 
 config VARIANT_DIR
-	default "tgl"
+	default "cml" if BOARD_STARLABS_LABTOP_CML
+	default "tgl" if BOARD_STARLABS_STARBOOK_TGL
 
 endif
diff --git a/src/mainboard/starlabs/labtop/Kconfig.name b/src/mainboard/starlabs/labtop/Kconfig.name
index b3a5742eb1..d00582f8aa 100644
--- a/src/mainboard/starlabs/labtop/Kconfig.name
+++ b/src/mainboard/starlabs/labtop/Kconfig.name
@@ -1,4 +1,7 @@
 comment "Star Labs LabTop Series"
 
+config BOARD_STARLABS_LABTOP_CML
+	bool "Star Labs LabTop Mk IV (i3-10110U and i7-10710U)"
+
 config BOARD_STARLABS_STARBOOK_TGL
 	bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)"
diff --git a/src/mainboard/starlabs/labtop/Makefile.inc b/src/mainboard/starlabs/labtop/Makefile.inc
index 71fc0cf282..dc26be0afa 100644
--- a/src/mainboard/starlabs/labtop/Makefile.inc
+++ b/src/mainboard/starlabs/labtop/Makefile.inc
@@ -1,6 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += ./spd
 subdirs-y += variants/$(VARIANT_DIR)
 
 bootblock-y += bootblock.c
diff --git a/src/mainboard/starlabs/labtop/dsdt.asl b/src/mainboard/starlabs/labtop/dsdt.asl
index ac6bc433de..c43e0482bd 100644
--- a/src/mainboard/starlabs/labtop/dsdt.asl
+++ b/src/mainboard/starlabs/labtop/dsdt.asl
@@ -17,10 +17,16 @@ DefinitionBlock(
 
 	Device (\_SB.PCI0)
 	{
+#if CONFIG(SOC_INTEL_CANNONLAKE_BASE)
+		/* Comet Lake */
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+#elif CONFIG(SOC_INTEL_TIGERLAKE)
 		/* Tiger Lake */
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
+#endif
 
 		/* PS/2 Keyboard */
 		#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/starlabs/labtop/spd/Makefile.inc b/src/mainboard/starlabs/labtop/spd/Makefile.inc
new file mode 100644
index 0000000000..9e7f4e377e
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/spd/Makefile.inc
@@ -0,0 +1,21 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# Schematics for this platform show Samsung K4A8G165WB-BCRC devices
+# which are 8Gb, 2400Mbps 512Mx16 devices.
+#
+# The hardware platforms used for testing are fitted with a Micron part
+# which has the FBGA identifier "D9ZFW".  The identification tool at
+# https://www.micron.com/support/tools-and-utilities/fbga identifies
+# this as the MT40A1G16KD-062E:E.  These are 16Gb, 1Gx16 devices.
+#
+# We have defined both SPD options below.
+SPD_SOURCES = empty_ddr4			# 0b0000
+SPD_SOURCES += micron-MT40A1G16KD-062E-E	# 0b0001
+SPD_SOURCES += empty_ddr4			# 0b0010
+SPD_SOURCES += empty_ddr4			# 0b0011
+SPD_SOURCES += empty_ddr4			# 0b0100
+SPD_SOURCES += empty_ddr4			# 0b0101
+SPD_SOURCES += samsung-K4A8G165WB-BCRC		# 0b0110
+SPD_SOURCES += samsung-K4A8G165WB-BCRC		# 0b0111
+
+LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
diff --git a/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex
new file mode 100644
index 0000000000..67b46cd239
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex
new file mode 100644
index 0000000000..17778473af
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex
@@ -0,0 +1,33 @@
+# Micron MT40A1G16KD-062E:E
+23 11 0C 03 46 29 00 08  00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 2B 00  6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34  28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5  00 00 00 00 E7 00 7C A0
+0F 01 1F 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 21 7D
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+80 2C 00 00 00 00 00 00  00 4D 54 34 30 41 31 47
+31 36 4B 44 2D 30 36 32  45 3A 45 20 20 31 80 2C
+45 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex
new file mode 100644
index 0000000000..36b85a2035
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex
@@ -0,0 +1,33 @@
+# K4A8G165WB-BCRC
+23 11 0C 03 45 21 00 08  00 60 00 03 02 03 00 00
+00 00 07 0D F8 0F 00 00  6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34  28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36  0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5  00 00 00 00 E7 D6 0B E3
+0F 11 02 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00  00 4D 34 37 31 41 35 32
+34 34 42 42 30 2D 43 52  43 20 20 20 20 00 80 CE
+FF 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
diff --git a/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc
new file mode 100644
index 0000000000..2a505c35c7
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += romstage.c
+
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/starlabs/labtop/variants/cml/board.fmd b/src/mainboard/starlabs/labtop/variants/cml/board.fmd
new file mode 100644
index 0000000000..9018104edd
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/board.fmd
@@ -0,0 +1,14 @@
+#
+# Manually defined FMD in order to ensure that space is reserved for the EC
+# at the top of the BIOS region.
+#
+FLASH 16M {
+	BIOS@0x400000 0xC00000 {
+		EC@0x0 0x20000
+		RW_MRC_CACHE@0x20000 0x10000
+		SMMSTORE@0x30000 0x40000
+		CONSOLE@0x70000 0x20000
+		FMAP@0x90000 0x200
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/starlabs/labtop/variants/cml/data.vbt b/src/mainboard/starlabs/labtop/variants/cml/data.vbt
new file mode 100644
index 0000000000..4b31c96aad
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/data.vbt
diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
new file mode 100644
index 0000000000..c0077a4128
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb
@@ -0,0 +1,195 @@
+chip soc/intel/cannonlake
+	# CPU
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable"			= "1"
+
+	# Graphics
+	# IGD Displays
+	register "panel_cfg" = "{
+		.up_delay_ms			=  0,				// T3
+		.backlight_on_delay_ms		=  0,				// T7
+		.backlight_off_delay_ms		=  0,				// T9
+		.down_delay_ms			=  0,				// T10
+		.cycle_delay_ms			=  500,				// T12
+		.backlight_pwm_hz		=  200,				// PWM
+	}"
+
+	# FSP Memory
+	register "enable_c6dram"		= "1"
+	register "SaGv"				= "SaGv_Enabled"
+
+	# FSP Silicon
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+		[PchSerialIoIndexI2C4]		= PchSerialIoSkipInit,
+		[PchSerialIoIndexUART2]		= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "PchPmSlpS3MinAssert"		= "2"				# 50ms
+	register "PchPmSlpS4MinAssert"		= "3"				# 1s
+	register "PchPmSlpSusMinAssert"		= "3"				# 500ms
+	register "PchPmSlpAMinAssert"		= "3"				# 2s
+
+	# Thermal
+	register "tcc_offset"			= "10"
+
+	# PM Util
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0"			= "PMC_GPP_B"
+	register "gpe0_dw1"			= "PMC_GPP_C"
+	register "gpe0_dw2"			= "PMC_GPP_E"
+
+	# PCIe Clock
+	register "PcieClkSrcClkReq[0]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[3]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]"		= "PCIE_CLK_NOTUSED"
+
+# Actual device tree.
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end						# Host Bridge
+		device pci 02.0 on  end						# Integrated Graphics Device
+		device pci 04.0 on						# SA Thermal Device
+			register "Device4Enable"		= "1"
+		end
+		device pci 12.0 off end						# Thermal Subsystem
+		device pci 12.5 off end						# UFS SCS
+		device pci 12.6 off end						# GSPI #2
+		device pci 14.0 on						# USB xHCI
+			### USB 2.0 Devices
+			# Motherboard USB Type C
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard SD Card
+			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb2_ports[5]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Webcam
+			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Bluetooth
+			register "usb2_ports[9]"		= "USB2_PORT_MID(OC_SKIP)"
+
+			### USB 3.0 Devices
+			# Motherboard USB Type C
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+		end
+		device pci 14.1 off end						# USB xDCI (OTG)
+		device pci 14.3 on						# CNVi
+			chip drivers/wifi/generic
+				register "wake"			= "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device pci 14.5 off end						# SDCard
+		device pci 15.0 on						# I2C0
+			chip drivers/i2c/hid
+				register "generic.hid"		= ""STAR0001""
+				register "generic.desc"		= ""Touchpad""
+				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
+				register "generic.probed"	= "1"
+				register "hid_desc_reg_offset"	= "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 off end						# I2C1
+		device pci 15.2 off end						# I2C2
+		device pci 15.3 off end						# I2C3
+		device pci 16.0 on  end						# Management Engine Interface 1
+		device pci 16.1 off end						# Management Engine Interface 2
+		device pci 16.2 off end						# Management Engine IDE-R
+		device pci 16.3 off end						# Management Engine KT Redirection
+		device pci 16.4 off end						# Management Engine Interface 3
+		device pci 16.5 off end						# Management Engine Interface 4
+		device pci 17.0 on						# SATA
+			register "SataSalpSupport"		= "1"
+			# Port 1
+			register "SataPortsEnable[1]"		= "1"
+			register "SataPortsDevSlp[1]"		= "1"
+		end
+		device pci 19.0 on  end						# I2C4
+		device pci 19.1 off end						# I2C5
+		device pci 19.2 on  end						# UART #2
+		device pci 1a.0 off end						# eMMC
+		device pci 1c.0 off end						# PCI Express Port 1
+		device pci 1c.1 off end						# PCI Express Port 2
+		device pci 1c.2 off end						# PCI Express Port 3
+		device pci 1c.3 off end						# PCI Express Port 4
+		device pci 1c.4 off end						# PCI Express Port 5
+		device pci 1c.5 off end						# PCI Express Port 6
+		device pci 1c.6 off end						# PCI Express Port 7
+		device pci 1c.7 off end						# PCI Express Port 8
+		device pci 1d.0 on						# PCI Express Port 9 (SSD x4)
+			register "PcieRpSlotImplemented[8]"	= "1"
+			register "PcieRpEnable[8]"		= "1"
+			register "PcieRpLtrEnable[8]"		= "1"
+			register "PcieClkSrcUsage[1]"		= "0x08"
+			register "PcieClkSrcClkReq[1]"		= "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off end						# PCI Express Port 10
+		device pci 1d.2 off end						# PCI Express Port 11
+		device pci 1d.3 off end						# PCI Express Port 12
+		device pci 1e.0 off end						# UART #0
+		device pci 1e.1 off end						# UART #1
+		device pci 1e.2 off end						# GSPI #0
+		device pci 1e.3 off end						# GSPI #1
+		device pci 1f.0 on						# LPC Interface
+			register "gen1_dec"			= "0x000c0681"
+			register "gen2_dec"			= "0x000c1641"
+			register "gen3_dec"			= "0x00fc0201"
+			register "gen4_dec"			= "0x000c0081"
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.00 on  end			# IO Interface
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 on				# PS/2 Keyboard
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
+				end
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device pci 1f.1 off end						# P2SB
+		device pci 1f.2 hidden end					# Power Management Controller
+		device pci 1f.3 on						# Intel HDA
+			subsystemid 0x10ec 0x1200
+			register "PchHdaAudioLinkHda"		= "1"
+		end
+		device pci 1f.4 on  end						# SMBus
+		device pci 1f.5 on  end						# PCH SPI
+		device pci 1f.6 off end						# GbE
+	end
+	chip drivers/crb
+		device mmio 0xfed40000 on end
+	end
+end
diff --git a/src/mainboard/starlabs/labtop/variants/cml/devtree.c b/src/mainboard/starlabs/labtop/variants/cml/devtree.c
new file mode 100644
index 0000000000..cf0734e4ce
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/devtree.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <option.h>
+#include <types.h>
+#include <variants.h>
+
+void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+
+	struct soc_power_limits_config *soc_conf = &cfg->power_limits_config;
+
+	struct device *nic_dev = pcidev_on_root(0x14, 3);
+
+	/* Update PL1 & PL2 based on CMOS settings */
+	switch (get_uint_option("power_profile", 0)) {
+	case 1:
+		soc_conf->tdp_pl1_override = 17;
+		soc_conf->tdp_pl2_override = 20;
+		break;
+	case 2:
+		soc_conf->tdp_pl1_override = 20;
+		soc_conf->tdp_pl2_override = 25;
+		break;
+	default:
+		disable_turbo();
+		soc_conf->tdp_pl1_override = 15;
+		soc_conf->tdp_pl2_override = 15;
+		break;
+	}
+
+	/* Enable/Disable Wireless based on CMOS settings */
+	if (get_uint_option("wireless", 1) == 0)
+		nic_dev->enabled = 0;
+
+	/* Enable/Disable Webcam based on CMOS settings */
+	if (get_uint_option("webcam", 1) == 0)
+		cfg->usb2_ports[3].enable = 0;
+}
diff --git a/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads
new file mode 100644
index 0000000000..8402b39a94
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,   -- USB-C
+      HDMI1, -- USB-C
+      HDMI2, -- HDMI
+      eDP,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/starlabs/labtop/variants/cml/gpio.c b/src/mainboard/starlabs/labtop/variants/cml/gpio.c
new file mode 100644
index 0000000000..e29cd8199b
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/gpio.c
@@ -0,0 +1,414 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variants.h>
+
+/*
+ * All definitions are taken from a comparison of the output of "inteltool -a"
+ * using the stock BIOS and with coreboot.
+ */
+
+/* Early pad configuration in bootblock */
+const struct pad_config early_gpio_table[] = {
+	/* C20:	 UART2_RXD			*/
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* C21:	 UART2_TXD			*/
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* E22:	BRD_ID0				*/
+	PAD_CFG_GPO(GPP_E22, 1, PLTRST),
+	/* E23:	BRD_ID1				*/
+	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
+	/* H6:	BRD_ID2				*/
+	PAD_CFG_GPI(GPP_H6, NONE, PLTRST),
+	/* H7:	BRD_ID3				*/
+	PAD_CFG_GPI(GPP_H7, NONE, PLTRST),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage. */
+const struct pad_config gpio_table[] = {
+	/* REFERENCE:	EP PER SCHEMATIC	*/
+
+	/* GPD0:	PCH_BATLOW#		*/
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1:	AC_PRESENT		*/
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2:	LAN_WAKE#		*/
+	PAD_NC(GPD2, NONE),
+	/* GPD3:	SIO_PWRBTN#		*/
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+	/* GPD4:	SIO_SLP_S3#		*/
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5:	SIO_SLP_S4#		*/
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6:	SIO_SLP_A#		*/
+	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+	/* GPD7:	PCH_TBT_PERST#		*/
+	PAD_CFG_GPO(GPD7, 0, PLTRST),
+	/* GPD8:	SUSCLK			*/
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9:	SIO_SLP_WLAN#		*/
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	/* GPD10:	SIO_SLP_S5#		*/
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+	/* GPD11:	PM_LANPHY_EN		*/
+	PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+
+	/* A0:	KBRST_N			*/
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+	/* A1:	LPC_AD0				*/
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+	/* A2:	LPC_AD1				*/
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+	/* A3:	LPC_AD2				*/
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+	/* A4:	LPC_AD3				*/
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+	/* A5:	LPC_FRAME_N			*/
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+	/* A6:	LPC_SERIRQ			*/
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	/* A7:	Not Connected			*/
+	PAD_NC(GPP_A7, NONE),
+	/* A8:	 GPPC_A8_CLKRUN_N		*/
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+	/* A9:	 ESPI_CLK			*/
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	/* A10:	Not Connected			*/
+	PAD_NC(GPP_A10, NONE),
+	/* A11:	Not Connected			*/
+	PAD_NC(GPP_A11, NONE),
+	/* A12:	 TABLET_MODE_CTRL		*/
+	PAD_NC(GPP_A12, NONE),
+	/* A13:	 SUSPWRDNACK			*/
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+	/* A14:	 PM_SUS_STAT_N			*/
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15:	 SPK_PD_N			*/
+	PAD_CFG_GPO(GPP_A15, 1, PLTRST),
+	/* A16:	Not Connected			*/
+	PAD_NC(GPP_A16, NONE),
+	/* A17:	 SAR_DPR_PCH			*/
+	PAD_NC(GPP_A17, NONE),
+	/* A18:	 ACCEL1_INT1			*/
+	PAD_NC(GPP_A18, UP_20K),
+	/* A19:	 ACCEL2_INT1			*/
+	PAD_NC(GPP_A19, UP_20K),
+	/* A20:	 HUMAN_PRESENCE_INT_N		*/
+	PAD_NC(GPP_A20, UP_20K),
+	/* A21:	 HALL_SENSOR_INT		*/
+	PAD_NC(GPP_A21, UP_20K),
+	/* A22:	 SAR_NIRQ_PCH			*/
+	PAD_NC(GPP_A22, UP_20K),
+	/* A23:	 INT_SHARED			*/
+	PAD_NC(GPP_A23, UP_20K),
+
+	/* B0:	Not Connected			*/
+	PAD_NC(GPP_B0, NONE),
+	/* B1:	Not Connected			*/
+	PAD_NC(GPP_B1, NONE),
+	/* B2:	Not Connected			*/
+	PAD_NC(GPP_B2, NONE),
+	/* B3:	CLICK_PAD_INT_R_N		*/
+	PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST),
+	/* B4:	BT_RF_KILL_N			*/
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* B5:	 WLAN_CLKREQ#			*/
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	/* B6:	 CLKREQ1_SSD_N			*/
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	/* B7:	 LAN_CLKREQ#			*/
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+	/* B8:	Not Connected			*/
+	PAD_NC(GPP_B8, NONE),
+	/* B9:	Not Connected			*/
+	PAD_NC(GPP_B9, NONE),
+	/* B10:	Not Connected			*/
+	PAD_NC(GPP_B10, NONE),
+	/* B11:	 EXT_PWR_GATE_N			*/
+	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
+	/* B12:	 PM_SLP_S0_N			*/
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13:	 PLT_RST_N			*/
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* B14:	 TCH_PNL_PWR_EN			*/
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+	/* B15:	Not Connected			*/
+	PAD_NC(GPP_B15, NONE),
+	/* B16:	 FPS_INT			*/
+	PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),
+	/* B17:	 FPS_RST_N			*/
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST),
+	/* B18:	 AR_CIO_PWR_EN			*/
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	/* B19:	 GSPI1_CS0_FPS_N		*/
+	PAD_NC(GPP_B19, NONE),
+	/* B20:	 GSPI1_CLK_FPS			*/
+	PAD_NC(GPP_B20, NONE),
+	/* B21:	 GSPI1_MISO_FPS			*/
+	PAD_NC(GPP_B21, NONE),
+	/* B22:	 GSPI1_MOSI_FPS			*/
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	/* B23:	 EC_SLP_S0IX_N			*/
+	PAD_NC(GPP_B23, NONE),
+
+	/* C0:	 SMB_CLK			*/
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	/* C1:	 SMB_DATA			*/
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	/* C2:	 WIFI_RF_KILL_N			*/
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
+	/* C3:	Not Connected			*/
+	PAD_NC(GPP_C3, NONE),
+	/* C4:	Not Connected			*/
+	PAD_NC(GPP_C4, NONE),
+	/* C5:	 SML0ALERT			*/
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	/* C6:	Not Connected			*/
+	PAD_NC(GPP_C6, NONE),
+	/* C7:	Not Connected			*/
+	PAD_NC(GPP_C7, NONE),
+	/* C8:	 CODEC_INT_N			*/
+	PAD_CFG_GPI_APIC_LOW(GPP_C8, UP_20K, PLTRST),
+	/* C9:	Not Connected			*/
+	PAD_NC(GPP_C9, NONE),
+	/* C10:	Not Connected			*/
+	PAD_NC(GPP_C10, NONE),
+	/* C11:	Not Connected			*/
+	PAD_NC(GPP_C11, NONE),
+	/* C12:	 PCIE_NAND_RST_R_N		*/
+	PAD_CFG_GPO(GPP_C12, 1, PLTRST),
+	/* C13:	 M2_SSD_PWREN			*/
+	PAD_NC(GPP_C13, NONE),
+	/* C14:	 TBT_WAKE_MUX_SEL_N		*/
+	PAD_NC(GPP_C14, NONE),
+	/* C15:	 TBT_RST_N			*/
+	PAD_NC(GPP_C15, NONE),
+	/* C16:	 I2C0_SDA			*/
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* C17:	 I2C0_SCL			*/
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* C18:	 TOUCH_I2C_SDA			*/
+	PAD_NC(GPP_C18, NONE),
+	/* C19:	 TOUCH_I2C_SDL			*/
+	PAD_NC(GPP_C19, NONE),
+	/* C22:	 AR1_USB_PWR_EN			*/
+	PAD_NC(GPP_C22, NONE),
+	/* C23:	Not Connected			*/
+	PAD_NC(GPP_C23, NONE),
+
+	/* D0:	 TPM_IRQ			*/
+	PAD_NC(GPP_D0, NONE),
+	/* D1:	Not Connected			*/
+	PAD_NC(GPP_D1, NONE),
+	/* D2:	Not Connected			*/
+	PAD_NC(GPP_D2, NONE),
+	/* D3:	Not Connected			*/
+	PAD_NC(GPP_D3, NONE),
+	/* D4:	Not Connected			*/
+	PAD_NC(GPP_D4, NONE),
+	/* D5:	Not Connected			*/
+	PAD_NC(GPP_D5, NONE),
+	/* D6:	Not Connected			*/
+	PAD_NC(GPP_D6, NONE),
+	/* D7:	 ISH_I2C1_SDA			*/
+	PAD_NC(GPP_D7, NONE),
+	/* D8:	 ISH_I2C1_SDL			*/
+	PAD_NC(GPP_D8, NONE),
+	/* D9:	 TCH_PNL2_RST_R_N		*/
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+	/* D10:	 TCH_PNL2_INT_R_N		*/
+	PAD_NC(GPP_D10, NATIVE),
+	/* D11:	Not Connected			*/
+	PAD_NC(GPP_D11, NATIVE),
+	/* D12:	 GPPC_D_12			*/
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),
+	/* D13:	 WWAN_FCP_OFF_N			*/
+	PAD_NC(GPP_D13, NONE),
+	/* D14:	 TCH_PNL1_RST_N			*/
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	/* D15:	Not Connected			*/
+	PAD_NC(GPP_D15, NONE),
+	/* D16:	 GPIO_2_EC			*/
+	PAD_CFG_GPO(GPP_D16, 0, PWROK),
+	/* D17:	 DMIC_CLK1_SNDW3_CLK		*/
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	/* D18:	 DMIC_DATA1_SNDW3_DATA		*/
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	/* D19:	 DMIC_CLK_0			*/
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+	/* D20:	 DMIC_DATA_0			*/
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	/* D21:	Not Connected			*/
+	PAD_NC(GPP_D21, NONE),
+	/* D22:	 TPM_RST			*/
+	PAD_NC(GPP_D22, NONE),
+	/* D23:	 TPM_IRQ			*/
+	PAD_NC(GPP_D23, NONE),
+
+	/* E0:	Not Connected			*/
+	PAD_NC(GPP_E0, NONE),
+	/* E1:	 GPPC_E1_SATAXPCIE_1_SATAGP_1	*/
+	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+	/* E2:	Not Connected			*/
+	PAD_NC(GPP_E2, NONE),
+	/* E3:	Not Connected			*/
+	PAD_NC(GPP_E3, NONE),
+	/* E4:	Not Connected			*/
+	PAD_NC(GPP_E4, NONE),
+	/* E5:	 GPPC_E5_SATA_DEVSLP_1		*/
+	PAD_NC(GPP_E5, NONE),
+	/* E6:	Not Connected			*/
+	PAD_NC(GPP_E6, NONE),
+	/* E7:	Not Connected			*/
+	PAD_CFG_GPI(GPP_E7, NONE, PLTRST),
+	/* E8:	Not Connected			*/
+	PAD_NC(GPP_E8, NONE),
+	/* E9:	 GPPC_E9_USB2_OCB_0		*/
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* E10:	 GPPC_E10_USB2_OCB_1		*/
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	/* E11:	 USB2_P3_WP2_OC_N		*/
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	/* E12:	 GPPC_E12_USB2_OCB_3		*/
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* E13:	 DDI1_HPD			*/
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* E14:	 DDI2_HPD			*/
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15:	 SMC_SMI_N			*/
+	PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE),
+	/* E16:	 SMC_SCI_N			*/
+	PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL),
+	/* E17:	 EDP_HPD			*/
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+	/* E18:	 DDI1_DDC_SCL			*/
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+	/* E19:	 DDI1_DDC_SDA			*/
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+	/* E20:	 DDI2_CTRL_CLK			*/
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	/* E21:	 DDI2_CTRL_DATA			*/
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* F0:	Not Connected			*/
+	PAD_NC(GPP_F0, NONE),
+	/* F1:	Not Connected			*/
+	PAD_NC(GPP_F1, NONE),
+	/* F2:	Not Connected			*/
+	PAD_NC(GPP_F2, NONE),
+	/* F3:	Not Connected			*/
+	PAD_NC(GPP_F3, NONE),
+	/* F4:	CNV_BRI_DT_R			*/
+	PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1),
+	/* F5:	CNV_BRI_RSP			*/
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
+	/* F6:	CNV_RGI_DT_R			*/
+	PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1),
+	/* F7:	CNV_RGI_RSP			*/
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
+	/* F8:	Not Connected			*/
+	PAD_NC(GPP_F8, NONE),
+	/* F9:	Not Connected			*/
+	PAD_NC(GPP_F9, NONE),
+	/* F10:	Not Connected			*/
+	PAD_NC(GPP_F10, NONE),
+	/* F11:	EMMC_CMD			*/
+	PAD_NC(GPP_F11, NONE),
+	/* F12:	EMMC_DATA_0			*/
+	PAD_NC(GPP_F12, NONE),
+	/* F13:	EMMC_DATA_1			*/
+	PAD_NC(GPP_F13, NONE),
+	/* F14:	EMMC_DATA_2			*/
+	PAD_NC(GPP_F14, NONE),
+	/* F15:	EMMC_DATA_3			*/
+	PAD_NC(GPP_F15, NONE),
+	/* F16:	EMMC_DATA_4			*/
+	PAD_NC(GPP_F16, NONE),
+	/* F17:	EMMC_DATA_5			*/
+	PAD_NC(GPP_F17, NONE),
+	/* F18:	EMMC_DATA_6			*/
+	PAD_NC(GPP_F18, NONE),
+	/* F19:	EMMC_DATA_7			*/
+	PAD_NC(GPP_F19, NONE),
+	/* F20:	EMMC_STROBE			*/
+	PAD_NC(GPP_F20, NONE),
+	/* F21:	EMMC_CLK			*/
+	PAD_NC(GPP_F21, NONE),
+	/* F22:	EMMC_RESETB			*/
+	PAD_NC(GPP_F22, NONE),
+	/* F23:	A4WP_PRESENT			*/
+	PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1),
+
+	/* G0:	Not Connected			*/
+	PAD_NC(GPP_G0, NONE),
+	/* G1:	Not Connected			*/
+	PAD_NC(GPP_G1, NONE),
+	/* G2:	Not Connected			*/
+	PAD_NC(GPP_G2, NONE),
+	/* G3:	Not Connected			*/
+	PAD_NC(GPP_G3, NONE),
+	/* G4:	Not Connected			*/
+	PAD_NC(GPP_G4, NONE),
+	/* G5:	Not Connected			*/
+	PAD_NC(GPP_G5, UP_20K),
+	/* G6:	Not Connected			*/
+	PAD_NC(GPP_G6, NONE),
+	/* G7:	Not Connected			*/
+	PAD_NC(GPP_G7, DN_20K),
+
+	/* H0:	Not Connected			*/
+	PAD_NC(GPP_H0, NONE),
+	/* H1:	 GPPC_H1_SSP2_SFRM		*/
+	PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3),
+	/* H2:	 GPPC_H2_SSP2_TXD		*/
+	PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3),
+	/* H3:	Not Connected			*/
+	PAD_NC(GPP_H3, UP_20K),
+	/* H4:	 GSENSOR_I2C_SDA		*/
+	PAD_NC(GPP_H4, NONE),
+	/* H5:	 GSENSOR_I2C_SCL		*/
+	PAD_NC(GPP_H5, NONE),
+	/* H8:	Not Connected			*/
+	PAD_NC(GPP_H8, NONE),
+	/* H9:	Not Connected			*/
+	PAD_NC(GPP_H9, NONE),
+	/* H10:	 ISH_I2C2_SDA			*/
+	PAD_CFG_GPO(GPP_H10, 1, PLTRST),
+	/* H11:	 ISH_I2C2_SCL			*/
+	PAD_CFG_GPO(GPP_H11, 1, PLTRST),
+	/* H12:	Not Connected			*/
+	PAD_NC(GPP_H12, NONE),
+	/* H13:	Not Connected			*/
+	PAD_NC(GPP_H13, NONE),
+	/* H14:	Not Connected			*/
+	PAD_NC(GPP_H14, NONE),
+	/* H15:	Not Connected			*/
+	PAD_NC(GPP_H15, NONE),
+	/* H16:	Not Connected			*/
+	PAD_NC(GPP_H16, NONE),
+	/* H17:	 GPPC_H_17_WWAN_DISABLE_N	*/
+	PAD_CFG_GPO(GPP_H17, 0, DEEP),
+	/* H18:	 GPPC_H_18_CPU_C10		*/
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19:	Not Connected			*/
+	PAD_NC(GPP_H19, NONE),
+	/* H20:	Not Connected			*/
+	PAD_NC(GPP_H20, NONE),
+	/* H21:	 GPPC_H21			*/
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+	/* H22:	Not Connected			*/
+	PAD_NC(GPP_H22, NONE),
+	/* H23:	 GPPC_H23			*/
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c b/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c
new file mode 100644
index 0000000000..76762a509c
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec1200, /* Subsystem ID */
+	38,	    /* Number of jacks (NID entries) */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID */
+	AZALIA_SUBVENDOR(0, 0x10ec1200),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x04ab1020),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x40700001),
+	AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
+
+	/* Reset to D0 */
+	0x00170500,
+	0x00170500,
+	0x00170500,
+	0x00170500,
+
+	/* Reset Register */
+	0x0205001A,
+	0x02048003,
+	0x0205001A,
+	0x0204C003,
+
+	/* ALC256 Default 1 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+
+	/* ALC256 Default 2 */
+	0x02050040,
+	0x02049800,
+	0x02050034,
+	0x0204023C,
+
+	/* ALC256 Default 3 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+
+	/* ALC256 Default 4 */
+	0x0205001B,
+	0x02040A4B,
+	0x02050008,
+	0x02046A6C,
+
+	/* Jack Detection */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+
+	/* Combo Jack TRS setting */
+	0x02050038,
+	0x02047901,
+
+	/* Disable Microphone Security */
+	0x0205000D,
+	0x0204A020,
+
+	/* Enable ADC clock */
+	0x02050005,
+	0x02040700,
+
+	/* Speaker Enable */
+	0x0205000C,
+	0x020401EF,
+
+	/*
+	 * Equalizer:
+	 *
+	 * AGC
+	 * Threshold:	- 6.00 dB
+	 * Front Boost:	+ 6.00 dB
+	 * Post Boost:	+ 6.00 dB
+	 *
+	 * Low Pass Filter
+	 * Boost Gain:	Enabled
+	 * BW:		200Hz
+	 * Gain:	+ 4.00 dB
+	 *
+	 * Band Pass Filter 1
+	 * Fc:		240Hz
+	 * BW:		400Hz
+	 * Gain:	- 4.00 dB
+	 *
+	 * Band Pass Filter 2
+	 * Fc:		16000Hz
+	 * BW:		1000Hz
+	 * Gain:	+ 12.00 dB
+	 *
+	 * High Pass Filter
+	 * Boost Gain:	Enabled
+	 * BW:		200Hz
+	 * Gain:	- 4.00 dB
+	 *
+	 * Class D Amp
+	 * Power:	2.5W
+	 * Resistance:	4ohms
+	 *
+	 * EQ Output
+	 * Left:	+ 0.00 dB
+	 * Right:	+ 0.00 dB
+	 *
+	 * VARQ
+	 * Q:		0.707
+	 */
+
+	0x05350000,
+	0x053404DA,
+	0x0535001d,
+	0x05340800,
+
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341F7A,
+
+	0x05350004,
+	0x0534FA18,
+	0x0535000F,
+	0x0534C295,
+
+	0x05350010,
+	0x05341D73,
+	0x05350011,
+	0x0534FA18,
+
+	0x05350012,
+	0x05341E08,
+	0x05350013,
+	0x05341C10,
+
+	0x05350014,
+	0x05342FB2,
+	0x0535001B,
+	0x05341F2C,
+
+	0x0535001C,
+	0x0534095C,
+	0x05450000,
+	0x05440000,
+
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+
+	0x05450003,
+	0x05441F7A,
+	0x05450004,
+	0x0544FA18,
+
+	0x0545000F,
+	0x0544C295,
+	0x05450010,
+	0x05441D73,
+
+	0x05450011,
+	0x0544FA18,
+	0x05450012,
+	0x05441E08,
+
+	0x05450013,
+	0x05441C10,
+	0x05450014,
+	0x05442FB2,
+
+	0x0545001B,
+	0x05441F2C,
+	0x0545001C,
+	0x0544095C,
+
+	0x05350000,
+	0x0534C4DA,
+	0x02050038,
+	0x02044901,
+
+	0x02050013,
+	0x0204422F,
+	0x02050016,
+	0x02044E50,
+
+	0x02050012,
+	0x0204EBC4,
+	0x02050020,
+	0x020451FF,
+
+	0x8086280b, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+	4,	    /* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/starlabs/labtop/variants/cml/romstage.c b/src/mainboard/starlabs/labtop/variants/cml/romstage.c
new file mode 100644
index 0000000000..189b7f378c
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/romstage.c
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <gpio.h>
+#include <option.h>
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+#include <string.h>
+#include <types.h>
+
+static unsigned int get_memory_config_straps(void)
+{
+	/*
+	 * The hardware supports a number of different memory configurations
+	 * which are selected using four ID bits ID3 (GPP_H7), ID2 (GPP_H6),
+	 * ID1 (GPP_E23) and ID0 (GPP_E22).
+	 *
+	 * The mapping is defined in the schematics as follows (ID3 is always
+	 * 0 and can be ignored):
+	 *
+	 * ID2	ID1	ID0	Memory type
+	 * -----------------------------------------------
+	 * 0	0	0	Hynix 16G dual channel
+	 * 0	0	1	Micron 16G dual channel
+	 * 0	1	0	Hynix 8G dual channel
+	 * 0	1	1	Hynix 4G single channel
+	 * 1	0	0	Micron 8G dual channel
+	 * 1	0	1	Micron 4G single channel
+	 * 1	1	0	Samsung 8G dual channel
+	 * 1	1	1	Samsung 4G single channel
+	 *
+	 * We return the value of these bits so that the index into the SPD
+	 * table can be .spd[] values can be configured correctly in the
+	 * memory configuration structure.
+	 */
+
+	gpio_t memid_gpios[] = {GPP_E22, GPP_E23, GPP_H6};
+	return (u8)gpio_base2_value(memid_gpios, ARRAY_SIZE(memid_gpios));
+}
+
+static bool is_dual_channel(const unsigned int memid)
+{
+	return memid != 3 && memid != 5 && memid != 7;
+}
+
+static void fill_spd_data(struct cnl_mb_cfg *mem_cfg)
+{
+	const unsigned int memid = get_memory_config_straps();
+	printk(BIOS_DEBUG, "Memory config straps: 0x%.2x\n", memid);
+	/*
+	 * If we are using single channel ID = 3, 5 or 7 then we only
+	 * populate .spd[0].If we are dual channel then we also populate
+	 * .spd[2] as well.
+	 */
+	mem_cfg->spd[0].read_type = READ_SPD_CBFS;
+	mem_cfg->spd[0].spd_spec.spd_index = memid;
+	if (is_dual_channel(memid)) {
+		mem_cfg->spd[2].read_type = READ_SPD_CBFS;
+		mem_cfg->spd[2].spd_spec.spd_index = memid;
+	}
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	struct cnl_mb_cfg memcfg = {
+		.rcomp_resistor = {121, 81, 100},
+		.rcomp_targets = {100, 40, 20, 20, 26},
+		.dq_pins_interleaved = 0,
+		.vref_ca_config = 2,
+		.ect = 0,
+	};
+
+	const uint8_t vtd = get_uint_option("vtd", 1);
+	memupd->FspmTestConfig.VtdDisable = !vtd;
+
+	const uint8_t ht =
+		get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading);
+	memupd->FspmConfig.HyperThreading = ht;
+
+	fill_spd_data(&memcfg);
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}