soc/intel/xeon_sp: Use common _CRS code generation

Drop SoC specific code and use generic implementation provided
by pci_domain_fill_ssdt.

TEST=Booted on IBM/SBP1 to Ubuntu 22.04.
TEST=intel/archercity CRB

Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80796
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

8 files changed, 13 insertions, 424 deletions

diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c
index 853b6bf918..b461f0e05d 100644
--- a/src/soc/intel/xeon_sp/chip_common.c
+++ b/src/soc/intel/xeon_sp/chip_common.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <acpi/acpigen_pci.h>
 #include <assert.h>
 #include <console/console.h>
 #include <device/pci.h>
@@ -243,6 +244,7 @@ static struct device_operations iio_pcie_domain_ops = {
 #if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name        = soc_acpi_name,
 	.write_acpi_tables = northbridge_write_acpi_tables,
+	.acpi_fill_ssdt	   = pci_domain_fill_ssdt,
 #endif
 };
 
@@ -257,6 +259,7 @@ static struct device_operations ubox_pcie_domain_ops = {
 #if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name        = soc_acpi_name,
 	.write_acpi_tables = northbridge_write_acpi_tables,
+	.acpi_fill_ssdt	   = pci_domain_fill_ssdt,
 #endif
 };
 
@@ -348,6 +351,7 @@ static struct device_operations iio_cxl_domain_ops = {
 #if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name        = soc_acpi_name,
 	.write_acpi_tables = northbridge_write_acpi_tables,
+	.acpi_fill_ssdt	   = pci_domain_fill_ssdt,
 #endif
 };
 
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 8a828c677e..1fc9c7530b 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-
+#include <acpi/acpigen_pci.h>
 #include <arch/ioapic.h>
 #include <console/console.h>
 #include <console/debug.h>
diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
index 8b24ba2b52..b2d6d79412 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
@@ -43,72 +43,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 void uncore_fill_ssdt(const struct device *device)
 {
-	struct iiostack_resource stack_info = {0};
-
-	/* Only add RTxx entries once. */
-	if (device->upstream->secondary != 0 || device->upstream->segment_group != 0)
-		return;
-
-	get_iiostack_info(&stack_info);
-
-	for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) {
-		const STACK_RES *ri = &stack_info.res[stack];
-		char rtname[16];
-
-		snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", stack);
-		acpigen_write_scope(rtname);
-
-		acpigen_write_name("_CRS");
-		printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n",
-			rtname, stack);
-
-		acpigen_write_resourcetemplate_header();
-
-		/* bus resource */
-		acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit,
-			0x0, (ri->BusLimit - ri->BusBase + 1));
-
-		/* additional io resources on socket 0 bus 0 */
-		if (stack == 0) {
-			/* ACPI 6.4.2.5 I/O Port Descriptor */
-			acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
-
-			/* IO decode  CF8-CFF */
-			acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
-			acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
-			acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
-			acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
-		}
-
-		/* IO resource */
-		acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
-			ri->PciResourceIoLimit, 0x0,
-			(ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
-
-		/* additional mem32 resources on socket 0 bus 0 */
-		if (stack == 0) {
-			acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
-				VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
-			acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
-				(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
-				SPI_BASE_SIZE);
-		}
-
-		/* Mem32 resource */
-		acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
-			ri->PciResourceMem32Limit, 0x0,
-			(ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
-
-		/* Mem64 resource */
-		acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base,
-			ri->PciResourceMem64Limit, 0x0,
-			(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
-
-		acpigen_write_resourcetemplate_footer();
-
-		/* Scope */
-		acpigen_pop_len();
-	}
 }
 
 /* TODO: See if we can use the common generate_p_state_entries */
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index 1911e0609f..d8b31617e5 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
-
+#include <acpi/acpigen_pci.h>
 #include <cbfs.h>
 #include <console/console.h>
 #include <device/pci.h>
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c
index 2e2b14a2cc..b98e9989a6 100644
--- a/src/soc/intel/xeon_sp/skx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c
@@ -56,82 +56,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 void uncore_fill_ssdt(const struct device *device)
 {
-	const IIO_UDS *hob = get_iio_uds();
-
-	/* Only add RTxx entries once. */
-	if (device->upstream->secondary != 0)
-		return;
-
-	for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
-		if (!soc_cpu_is_enabled(socket))
-			continue;
-		iio++;
-		IIO_RESOURCE_INSTANCE iio_resource =
-			hob->PlatformData.IIO_resource[socket];
-		for (int stack = 0; stack <= PSTACK2; ++stack) {
-			const STACK_RES *ri = &iio_resource.StackRes[stack];
-			char rtname[16];
-
-			snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", socket * MAX_IIO_STACK + stack);
-			acpigen_write_scope(rtname);
-
-			acpigen_write_name("_CRS");
-
-			printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n",
-				rtname, socket, stack);
-
-			acpigen_write_resourcetemplate_header();
-
-			/* bus resource */
-			acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit,
-				0x0, (ri->BusLimit - ri->BusBase + 1));
-
-			// additional io resources on socket 0 bus 0
-			if (socket == 0 && stack == 0) {
-				/* ACPI 6.4.2.5 I/O Port Descriptor */
-				acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
-
-				/* IO decode  CF8-CFF */
-				acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF,
-					0, 0x03B0);
-				acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7,
-					0, 0x0918);
-				acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB,
-					0, 0x000C);
-				acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF,
-					0, 0x0020);
-			}
-
-			/* IO resource */
-			acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
-				ri->PciResourceIoLimit, 0x0,
-				(ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
-
-			// additional mem32 resources on socket 0 bus 0
-			if (socket == 0 && stack == 0) {
-				acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
-					VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
-				acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
-					(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
-					SPI_BASE_SIZE);
-			}
-
-			/* Mem32 resource */
-			acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
-				ri->PciResourceMem32Limit, 0x0,
-				(ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
-
-			/* Mem64 resource */
-			acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base,
-				ri->PciResourceMem64Limit, 0x0,
-				(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
-
-			acpigen_write_resourcetemplate_footer();
-
-			/* Scope */
-			acpigen_pop_len();
-		}
-	}
 }
 
 void soc_power_states_generation(int core, int cores_per_package)
diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c
index a9387f4237..7b934ba3a5 100644
--- a/src/soc/intel/xeon_sp/spr/chip.c
+++ b/src/soc/intel/xeon_sp/spr/chip.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-
+#include <acpi/acpigen_pci.h>
 #include <arch/ioapic.h>
 #include <console/console.h>
 #include <console/debug.h>
diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c
index 2b6aafa883..2e3baa3cb0 100644
--- a/src/soc/intel/xeon_sp/spr/ioat.c
+++ b/src/soc/intel/xeon_sp/spr/ioat.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-
+#include <acpi/acpigen_pci.h>
 #include <stdbool.h>
 
 #include <console/console.h>
@@ -26,6 +26,7 @@ static struct device_operations ioat_domain_ops = {
 #if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name        = soc_acpi_name,
 	.write_acpi_tables = northbridge_write_acpi_tables,
+	.acpi_fill_ssdt	   = pci_domain_fill_ssdt,
 #endif
 };
 
diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c
index ca1cdf993c..0b6e491fc0 100644
--- a/src/soc/intel/xeon_sp/spr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c
@@ -53,279 +53,11 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 	fill_fadt_extended_pm_io(fadt);
 }
 
-static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri,
-					 bool stack_enabled)
-{
-	/*
-	   Stacks 0 (TYPE_UBOX_IIO)
-		Scope: PC<socket><stack>, ResourceTemplate: P0RS
-	   Stacks 1 .. 5 (TYPE_UBOX_IIO)
-		Scope: PC<socket><stack>, ResourceTemplate: RBRS
-	*/
-	/* write _CRS scope */
-	char tres[16];
-	snprintf(tres, sizeof(tres), "\\_SB.PC%d%X", socket, stack);
-	acpigen_write_scope(tres);
-	acpigen_write_name("_CRS");
-
-	printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres,
-	       socket, stack);
-
-	acpigen_write_resourcetemplate_header();
-
-	/* Bus Resource */
-	if (stack_enabled) {
-		/* For stack with CXL device, the PCIe bus resource is BusBase only. */
-		if (is_iio_cxl_stack_res(ri))
-			acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1);
-		else
-			acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, 0x0,
-					      (ri->BusLimit - ri->BusBase + 1));
-	} else {
-		acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0);
-	}
-
-	/* Additional IO resources on socket 0 bus 0 */
-	if (socket == 0 && stack == 0) {
-		/* ACPI 6.4.2.5 I/O Port Descriptor */
-		acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
-
-		/* IO decode  CF8-CFF */
-		acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
-		acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
-		acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
-		acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
-	}
-
-	/* IO resource */
-	if (stack_enabled) {
-		acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
-				      ri->PciResourceIoLimit, 0x0,
-				      (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
-
-		/* Additional Mem32 resources on socket 0 bus 0 */
-		if (socket == 0 && stack == 0) {
-			acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
-					       VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
-			acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
-					       (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
-					       SPI_BASE_SIZE);
-		}
-
-		/* Mem32 resource */
-		acpigen_resource_dword(
-			0, 0xc, 1, 0, ri->PciResourceMem32Base, ri->PciResourceMem32Limit, 0x0,
-			(ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
-
-		/* Mem64 resource */
-		acpigen_resource_qword(
-			0, 0xc, 1, 0, ri->PciResourceMem64Base, ri->PciResourceMem64Limit, 0x0,
-			(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
-	} else {
-		/* Zeroed IO resource */
-		acpigen_resource_word(1, 0, 3, 0, 0, 0, 0, 0);
-
-		/* Zeroed Mem32 resource */
-		acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0);
-
-		/* Zeroed Mem64 resource */
-		acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0);
-	}
-
-	acpigen_write_resourcetemplate_footer();
-	acpigen_pop_len();
-}
-
-static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
-{
-	/*
-	   Stacks 1 .. 5 (TYPE_UBOX_IIO)
-		Scope: CX<socket><stack>, ResourceTemplate: RBRS
-	*/
-	/* write _CRS scope */
-	char tres[16];
-	snprintf(tres, sizeof(tres), "\\_SB.CX%d%X", socket, stack);
-	acpigen_write_scope(tres);
-	acpigen_write_name("_CRS");
-
-	printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres,
-	       socket, stack);
-
-	acpigen_write_resourcetemplate_header();
-
-	if (stack_enabled) {
-		/* bus resource, from (BusBase + 1) to BusLimit */
-		acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase + 1, ri->BusLimit, 0x0,
-				      (ri->BusLimit - ri->BusBase));
-
-		/* IO resource */
-		acpigen_resource_word(1, 0xc, 0x3, 0, ri->IoBase, ri->PciResourceIoBase - 1,
-				      0x0, ri->PciResourceIoBase - ri->IoBase);
-
-		/* Mem32 resource */
-		acpigen_resource_dword(0, 0xc, 1, 0, ri->Mmio32Base,
-				       ri->PciResourceMem32Base - 1, 0x0,
-				       ri->PciResourceMem32Base - ri->Mmio32Base);
-
-		/* Mem64 resource */
-		acpigen_resource_qword(0, 0xc, 1, 0, ri->Mmio64Base,
-				       ri->PciResourceMem64Base - 1, 0x0,
-				       ri->PciResourceMem64Base - ri->Mmio64Base);
-	} else {
-		/* bus resource, from (BusBase + 1) to BusLimit */
-		acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0);
-
-		/* IO resource */
-		acpigen_resource_word(1, 0, 3, 0, 0, 0, 0, 0);
-
-		/* Mem32 resource */
-		acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0);
-
-		/* Mem64 resource */
-		acpigen_resource_qword(0, 0, 1, 0, 0, 0, 0, 0);
-	}
-
-	acpigen_write_resourcetemplate_footer();
-	acpigen_pop_len();
-}
-
-static void create_dsdt_ioat_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
-{
-	if (!stack_enabled)
-		return;
-
-	/*
-	   Stacks 8 .. B (TYPE_DINO)
-		Scope: DI<socket><stack> for DINO, ResourceTemplate: DT
-		Scope: CP<socket><stack> for CPM (i.e., QAT), ResourceTemplate: MT
-		Scope: HQ<socket><stack> for HQM (i.e., DLB), ResourceTemplate: HT
-	*/
-
-	enum {
-		DSDT_DINO = 0,
-		DSDT_CPM,
-		DSDT_HQM,
-		DSDT_CPM1,
-		DSDT_HQM1
-	};
-	uint8_t rlist[] = {DSDT_DINO, DSDT_CPM, DSDT_HQM, DSDT_CPM1, DSDT_HQM1};
-
-	for (int i = 0; i < ARRAY_SIZE(rlist); ++i) {
-		uint8_t bus_base, bus_limit;
-		uint64_t mem64_base, mem64_limit;
-		char tres[16];
-
-		/* Note, This allocates the resources in a different order than
-		 * coreboot (DINO base is last). This causes the kernel to
-		 * reallocate the DINO BARs.
-		 * TODO: Use the resource settings from coreboot */
-		if (rlist[i] == DSDT_DINO) {
-			bus_base = ri->BusBase;
-			bus_limit = ri->BusBase;
-			mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE
-				     + CPM_MMIO_SIZE + HQM_MMIO_SIZE;
-			mem64_limit = ri->PciResourceMem64Limit;
-			snprintf(tres, sizeof(tres), "\\_SB.DI%d%X", socket, stack);
-		} else if (rlist[i] == DSDT_CPM) {
-			bus_base = ri->BusBase + CPM_BUS_OFFSET;
-			bus_limit = bus_base + CPM_RESERVED_BUS;
-			mem64_base = ri->PciResourceMem64Base;
-			mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
-			snprintf(tres, sizeof(tres), "\\_SB.PM%d%X", socket, stack);
-		} else if (rlist[i] == DSDT_HQM) {
-			bus_base = ri->BusBase + HQM_BUS_OFFSET;
-			bus_limit = bus_base + HQM_RESERVED_BUS;
-			mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE;
-			mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
-			snprintf(tres, sizeof(tres), "\\_SB.HQ%d%X", socket, stack);
-		} else if (rlist[i] == DSDT_CPM1) {
-			bus_base = ri->BusBase + CPM1_BUS_OFFSET;
-			bus_limit = bus_base + CPM_RESERVED_BUS;
-			mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE;
-			mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
-			snprintf(tres, sizeof(tres), "\\_SB.PN%d%X", socket, stack);
-		} else {
-			bus_base = ri->BusBase + HQM1_BUS_OFFSET;
-			bus_limit = bus_base + HQM_RESERVED_BUS;
-			mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE
-				     + CPM_MMIO_SIZE;
-			mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
-			snprintf(tres, sizeof(tres), "\\_SB.HR%d%X", socket, stack);
-		}
-
-		/* Note, some SKU doesn't provide CPM1 and HQM1 and owns smaller bus ranges
-		 accordingly*/
-		if (bus_limit > ri->BusLimit)
-			continue;
-
-		printk(BIOS_DEBUG,
-		       "\tCreating Dino ResourceTemplate %s for socket: %d, "
-		       "stack: %d\n bus_base:0x%x, bus_limit:0x%x\n",
-		       tres, socket, stack, bus_base, bus_limit);
-
-		acpigen_write_scope(tres);
-		acpigen_write_name("_CRS");
-		acpigen_write_resourcetemplate_header();
-
-		acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0,
-			(bus_limit - bus_base + 1));
-
-		/* Mem32 resource */
-		if (rlist[i] == DSDT_DINO)
-			acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
-				ri->PciResourceMem32Limit, 0x0,
-				(ri->PciResourceMem32Limit
-				- ri->PciResourceMem32Base + 1));
-
-		/* Mem64 resource */
-		acpigen_resource_qword(0, 0xc, 1, 0, mem64_base, mem64_limit, 0,
-			(mem64_limit - mem64_base + 1));
-
-		acpigen_write_resourcetemplate_footer();
-		acpigen_pop_len();
-	}
-}
-
-static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
-{
-	/*
-	   Stacks D .. E (TYPE_UBOX)
-		Scope: UC/UD<socket><0..1> for UBOX[1-2], ResourceTemplate: UT/UU
-	*/
-	for (int i = 0; i < 2; ++i) {
-		char tres[16];
-		/* write _CRS scope */
-		if (i == 0)
-			snprintf(tres, sizeof(tres), "\\_SB.UC%d%X", socket, stack);
-		else
-			snprintf(tres, sizeof(tres), "\\_SB.UD%d%X", socket, stack);
-
-		printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n",
-		       tres, socket, stack);
-
-		acpigen_write_scope(tres);
-		acpigen_write_name("_CRS");
-		acpigen_write_resourcetemplate_header();
-
-		if (!stack_enabled)
-			acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0);
-		else if (i == 0)
-			acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1);
-		else
-			acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase + 1, ri->BusBase + 1,
-					      0x0, 1);
-
-		acpigen_write_resourcetemplate_footer();
-		acpigen_pop_len();
-	}
-}
-
-
 /*
  * Add a DSDT ACPI Name field for STACK enable setting.
  *  This is retrieved by the device _STA defined in iiostack.asl
  */
-static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
+static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, bool stack_enabled)
 {
 	char stack_sta[16];
 	snprintf(stack_sta, sizeof(stack_sta), "ST%d%X", socket, stack);
@@ -375,17 +107,11 @@ void uncore_fill_ssdt(const struct device *device)
 			       __func__, socket, stack, ri->Personality);
 
 			if (stack <= IioStack5) { // TYPE_UBOX_IIO
-				create_dsdt_iou_pci_resource(socket, stack, ri, stack_enabled);
-				if (is_iio_cxl_stack_res(ri))
-					create_dsdt_iou_cxl_resource(socket, stack, ri,
-						stack_enabled);
-				create_dsdt_stack_sta(socket, stack, ri, stack_enabled);
+				create_dsdt_stack_sta(socket, stack, stack_enabled);
 			} else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO
-				create_dsdt_ioat_resource(socket, stack, ri, stack_enabled);
-				create_dsdt_stack_sta(socket, stack, ri, stack_enabled);
+				create_dsdt_stack_sta(socket, stack, stack_enabled);
 			} else if (stack == IioStack13) { // TYPE_UBOX
-				create_dsdt_ubox_resource(socket, stack, ri, stack_enabled);
-				create_dsdt_stack_sta(socket, stack, ri, stack_enabled);
+				create_dsdt_stack_sta(socket, stack, stack_enabled);
 			}
 		}
 	}