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authorFelix Held <felix-coreboot@felixheld.de>2022-02-02 22:54:05 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-03 23:46:17 +0000
commite04be37806dcf6494c876c278f7fd3da60b1242c (patch)
tree05eb64aba85b0fcacbd24f681268afae0f5c2bc0
parent556d1cc17f34615e3a08ccc9a48820a304a789a8 (diff)
mb/amd/chausie/devicetree: update I2C RX levels to match board design
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie5d5f5441132e5b0d8991d07d4dde994fc17ab64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
-rw-r--r--src/mainboard/amd/chausie/devicetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 6067b18ebf..8cc23e1d50 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -14,10 +14,10 @@ chip soc/amd/sabrina
}"
# I2C Pad Control RX Select Configuration
- register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V"
- register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V"
- register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V"
- register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V"
+ register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
+ register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
register "s0ix_enable" = "true"