Revert "soc/intel/adl: Skip sending MBP HOB to save boot time"

This reverts commit 9a7fbbc98e8610a0a5314470edd8d5dafe676a06.

SkipMbpHob UPD skips generation of MBP Hob within FSP. Skipping MBP
Hob generation also skips syncing correct version of chipset
data with CSE since FSP uses version information from MBP HOB.
In absence of MBP Hob, FSP is unable to get version information and
hence chipset data sync is skipped.

This creates an issue while platform tries to enter deeper sleep
states.

BUG=b:215448362
BRANCH=None
TEST= FSP can get version information from MBP HOB and chipset sync
is performed. It has been Verified using FSP debug logs on Brya
board.

Change-Id: I9a160fee72b61ae9eecababf9a16900e6bd4acff
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 0 insertions, 3 deletions

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 9a42642265..b92a5da417 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -207,9 +207,6 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
 	/* Skip GPIO configuration from FSP */
 	m_cfg->GpioOverride = 0x1;
 
-	/* Skip generation of MBP HOB from FSP. coreboot doesn't consume it */
-	m_cfg->SkipMbpHob = 1;
-
 	/* CNVi DDR RFI Mitigation */
 	m_cfg->CnviDdrRfim = config->CnviDdrRfim;
 }