diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 18:34:40 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 10:03:56 +0000 |
| commit | de341684368b15cf99966e4f7a5d5a5dcb85fe97 (patch) | |
| tree | 138dee4bdbd203cd49d0a9c94f7d5415e902ba44 | |
| parent | 411ae05f1daf2cc877eab76a7f961f735da2c861 (diff) | |
mb/google/slippy: Factor out common MRC settings
There's no need to redefine common settings.
Change-Id: I4c6b65bce42b875bb55e8d04da44afe9c18fb6e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
| -rw-r--r-- | src/mainboard/google/slippy/romstage.c | 43 |
1 files changed, 14 insertions, 29 deletions
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 2231921ce1..7e1520dbed 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -44,35 +44,20 @@ void mainboard_config_rcba(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data mainboard_pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, - .ec_present = 1, - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = 1, - }; - - *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ + pei_data->system_type = 5; /* ULT */ + pei_data->spd_addresses[0] = 0xff; + pei_data->spd_addresses[2] = 0xff; + pei_data->ec_present = 1; + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + pei_data->max_ddr3_freq = 1600; + pei_data->usb_xhci_on_resume = 1; variant_romstage_entry(pei_data); } |