diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-11-12 18:10:12 +0000 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-11-13 20:51:14 +0000 |
| commit | dada017748476569bfb621df9015cd79452c8540 (patch) | |
| tree | c33baaa5a45c9e657e014d52492aa6ebc757ac36 | |
| parent | 500ab1c6418edfda8dbd55435fe8795a8ecaee20 (diff) | |
mb/intel/saddlebrook: Make use of the chipset devicetree
Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: Ic4043828baf43d14f7f2060fa3946e3a9e2008fc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79038
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 67 |
1 files changed, 21 insertions, 46 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index ecb5e8c4f1..f2234a6937 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -198,51 +198,26 @@ chip soc/intel/skylake device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA thermal subsystem - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 - device pci 19.2 on end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 on end # UART #1 - device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device ref igpu on end + device ref south_xhci on end + device ref thermal on end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref uart2 on end + device ref i2c5 on end + device ref i2c4 on end + device ref pcie_rp1 on end + device ref uart0 on end + device ref uart1 on end + device ref gspi0 on end + device ref gspi1 on end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end end end |