diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2022-03-16 15:27:00 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-13 15:13:01 +0000 |
| commit | d8ea360d3ea1944e76fbbc36f35199a52160a9e6 (patch) | |
| tree | 90eaaa9afcc901aff10f5734b54a1bf5b3567a92 | |
| parent | 37c33052e5c32cfd732b149ec0748614ce5f0178 (diff) | |
soc/intel/alderlake: Add support for UFS controller
UFS(Universal Flash Storage) is the next generation storage standard and
a SCSI storage technology. It is also a successor of eMMC.
Following changes are needed to add support for UFS -
1) Add UFS controller to chipset.cb and keep it off by default
2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 09dc970298..caba2c06a6 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -118,6 +118,7 @@ chip soc/intel/alderlake device pci 10.7 alias thc1 off end device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end + device pci 12.7 alias ufs off end device pci 13.0 alias gspi3 off end device pci 14.0 alias xhci off chip drivers/usb/acpi diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 58f7579f7d..34e949066d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -642,6 +642,11 @@ static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, if (s_cfg->ScsEmmcEnabled) s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode; #endif + + /* UFS Configuration */ + s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */ + s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS); + /* Enable Hybrid storage auto detection */ s_cfg->HybridStorageMode = config->hybrid_storage_mode; } |