armv7: Reserve space BL1 and checksum header by specifying bootblock offset.

Not all ARM systems need "BL1", and the layout of BL* and bootblock may be
different (ex, Exynos 5250 may use a new BL1 with variable length checksum
header).

To support that better, define the real base address (and ROM offset) of boot
block, and then we can post-processing ROM image file by filling data / checksum
and any other information.

Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3664
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

7 files changed, 63 insertions, 41 deletions

diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index 27a0df6068..8474315458 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -48,7 +48,8 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 # TODO Change -b to Kconfig variable.
 $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
 	$(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
-		-B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \
+		-B $(objcbfs)/bootblock.bin -a 64 \
+		-b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \
 		-H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \
 		-o $(CONFIG_CBFS_ROM_OFFSET)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc
index bac32e21ff..b2c993af32 100644
--- a/src/arch/armv7/bootblock.inc
+++ b/src/arch/armv7/bootblock.inc
@@ -29,14 +29,6 @@
  * MA 02111-1307 USA
  */
 
-.section ".bl1", "a", %progbits
-_bl1:
-	/* For now we have to live with a first stage boot loader
-	 * on ARM, which is 8KB in size and it is prepended to the
-	 * reset vector
-	 */
-	.skip (CONFIG_BL1_SIZE_KB * 1024)
-
 .section ".start", "a", %progbits
 .globl _start
 _start: b	reset
diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds
index 6f6040dacb..837039653b 100644
--- a/src/arch/armv7/bootblock.lds
+++ b/src/arch/armv7/bootblock.lds
@@ -25,12 +25,11 @@ OUTPUT_ARCH(arm)
 TARGET(binary)
 SECTIONS
 {
-	ROMLOC = CONFIG_BOOTBLOCK_BASE - (CONFIG_BL1_SIZE_KB * 1024);
+	ROMLOC = CONFIG_BOOTBLOCK_BASE;
 
 	/* This section might be better named .setup */
 	.rom ROMLOC : {
 		_rom = .;
-		*(.bl1);
 		*(.start);
 		*(.id);
 		*(.text);
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index 5f5add4fc6..75d1178e31 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -10,9 +10,26 @@ config EXYNOS_ACE_SHA
 	bool
 	default n
 
-config BL1_SIZE_KB
-	int
-	default 8
+# ROM image layout.
+#
+# 0x0000: vendor-provided BL1 (8k).
+# 0x2000: bootblock
+#  0x2010-0x2090: reserved for CBFS master header.
+# 0xA000: Free for CBFS data.
+
+config BOOTBLOCK_ROM_OFFSET
+	hex
+	default 0x2000
+
+config CBFS_HEADER_ROM_OFFSET
+	hex "offset of master CBFS header in ROM"
+	default 0x2010
+
+config CBFS_ROM_OFFSET
+	# Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
+	hex "offset of CBFS data in ROM"
+	default 0x0A000
+
 
 # Example SRAM/iRAM map for Exynos5250 platform:
 #
@@ -50,17 +67,6 @@ config STACK_SIZE
 	hex
 	default 0x1000
 
-config CBFS_ROM_OFFSET
-	# Calculated by BL1 + max bootblock size.
-	hex "offset of CBFS data in ROM"
-	default 0x0A000
-
-# TODO Change this to some better address not overlapping bootblock when
-# cbfstool supports creating header in arbitrary location.
-config CBFS_HEADER_ROM_OFFSET
-	hex "offset of master CBFS header in ROM"
-	default 0x2040
-
 # TODO We may probably move this to board-specific implementation files instead
 # of KConfig values.
 config CBFS_CACHE_ADDRESS
diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig
index 93ece2e270..406ffd22e0 100644
--- a/src/cpu/samsung/exynos5420/Kconfig
+++ b/src/cpu/samsung/exynos5420/Kconfig
@@ -10,20 +10,39 @@ config EXYNOS_ACE_SHA
 	bool
 	default n
 
-config BL1_SIZE_KB
-	int
-	default 8
+# ROM image layout.
+#
+# 0x0000: vendor-provided BL1 (8k).
+# 0x2000: variable length bootblock checksum header
+# 0x2010: bootblock
+#  0x2020-0x20A0: reserved for CBFS master header.
+# 0xA000: Free for CBFS data.
+
+config BOOTBLOCK_ROM_OFFSET
+	hex
+	default 0x2010
+
+config CBFS_HEADER_ROM_OFFSET
+	hex "offset of master CBFS header in ROM"
+	default 0x2020
+
+config CBFS_ROM_OFFSET
+	# Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
+	hex "offset of CBFS data in ROM"
+	default 0x0A000
+
 
 # Example SRAM/iRAM map for Exynos5420 platform:
 #
 # 0x0202_0000: vendor-provided BL1
-# 0x0202_4400: bootblock, assume up to 32KB in size
+# 0x0202_4400: variable length bootblock checksum header.
+# 0x0202_4410: bootblock, assume up to 32KB in size
 # 0x0203_0000: romstage, assume up to 128KB in size.
 # 0x0207_4000: stack pointer
 
 config BOOTBLOCK_BASE
 	hex
-	default 0x02024400
+	default 0x02024410
 
 config ROMSTAGE_BASE
 	hex
@@ -50,17 +69,6 @@ config STACK_SIZE
 	hex
 	default 0x1000
 
-config CBFS_ROM_OFFSET
-	# Calculated by BL1 + max bootblock size.
-	hex "offset of CBFS data in ROM"
-	default 0x0A000
-
-# TODO Change this to some better address not overlapping bootblock when
-# cbfstool supports creating header in arbitrary location.
-config CBFS_HEADER_ROM_OFFSET
-	hex "offset of master CBFS header in ROM"
-	default 0x2040
-
 # TODO We may probably move this to board-specific implementation files instead
 # of KConfig values.
 config CBFS_CACHE_ADDRESS
diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig
index b66761d512..944e711c25 100644
--- a/src/mainboard/emulation/qemu-armv7/Kconfig
+++ b/src/mainboard/emulation/qemu-armv7/Kconfig
@@ -81,6 +81,10 @@ config ROMSTAGE_SIZE
 	hex
 	default 0x20000
 
+config BOOTBLOCK_ROM_OFFSET
+	hex
+	default 0x0
+
 config CBFS_HEADER_ROM_OFFSET
 	hex
 	default 0x0100000
diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig
index 1cde042f43..8651c9bf4b 100644
--- a/src/mainboard/ti/beaglebone/Kconfig
+++ b/src/mainboard/ti/beaglebone/Kconfig
@@ -54,6 +54,18 @@ config NR_DRAM_BANKS
 	int
 	default 1
 
+config BOOTBLOCK_ROM_OFFSET
+	hex
+	default 0x0
+
+config CBFS_HEADER_ROM_OFFSET
+	hex
+	default 0x10
+
+config CBFS_ROM_OFFSET
+	hex
+	default 0x5000
+
 choice CONSOLE_SERIAL_UART_CHOICES
 	prompt "Serial Console UART"
 	default CONSOLE_SERIAL_UART0