diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-10-26 17:03:25 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-07 14:16:05 +0000 |
| commit | d55ed57c36e02b5fa1ddd3526309fcfa9eeefe88 (patch) | |
| tree | 8921900ea05400fe5b1f70963150896ef4a2d3f1 | |
| parent | 00f227a21616f6b771b896ac117dcc9b341651c8 (diff) | |
mb/google/brya : Set EPP value for Vell board
The patch sets the EPP to 50% (0x80) for Vell. With EPP at 50%, the Vell
system demonstrated better power improvement without sacrificing the
performance.
PLT Results(Perf) with EPP@40% and EPP@50%:
EPP@40%: Device1-656 mins, Device2-664 mins.
EPP@50%: Device1-678 mins, Device2-677 mins.
In short, with EPP@50%, PLT KPI ran for more than 13 to 22mins compared
to EPP@40%.
Branch=firmware-brya-14505.B
BUG=b:215526166
TEST=Verified code build for Vell board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 98983ef03a..0c50eb422e 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -76,6 +76,10 @@ chip soc/intel/alderlake register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" register "sagv" = "SaGv_Enabled" + # Set EPP to 50%: 50 * 256 / 100 = 0x80 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x80" + # FIVR RFI Spread Spectrum 6% register "fivr_spread_spectrum" = "FIVR_SS_6" |